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    SILICON ON INSULATOR READ-WRITE NON-VOLATILE MEMORY COMPRISING LATERAL THYRISTOR AND TRAPPING LAYER
    3.
    发明公开
    SILICON ON INSULATOR READ-WRITE NON-VOLATILE MEMORY COMPRISING LATERAL THYRISTOR AND TRAPPING LAYER 有权
    SILIZIUM-AUF-ISOLATOR-LESE-SCHREIB-FESTSPEICHER MIT EINEM SEITLICHEN THYRISTOR UND EINER FALLENSCHICHT

    公开(公告)号：EP1743339A4

    公开(公告)日：2007-08-01

    申请号：EP05740193

    申请日：2005-04-28

    申请人： MICRON TECHNOLOGY INC

    发明人： BHATTACHARYYA ARUP

    IPC分类号： G11C11/39 ,  G11C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L27/102 ,  H01L27/12 ,  H01L29/74 ,  H01L29/749 ,  H01L29/768 ,  H01L29/87

    CPC分类号： H01L27/1027 ,  G11C11/39 ,  G11C16/349 ,  H01L21/28273 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87

    摘要： Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell (10) is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor (20) formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor (18), whose drain is connected to the bit line of the device, and which is gated by a first word line (14). A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0’. Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.

    摘要翻译： 这里公开了一种改进的基于晶闸管的存储单元。 在一个实施例中，使用绝缘体上硅（SOI）技术在浮动衬底中形成单元（10）。 该单元优选地包含完全形成在浮动衬底中并且由第二字线门控的横向晶闸管（20）。 晶闸管的阴极还包括存取晶体管（18）的源极，其漏极连接到器件的位线，并且由第一字线（14）门控。 俘获层被内置到浮动衬底中，并且当写入到单元中时，添加脉冲以使空穴捕获在俘获层上以获得逻辑状态'1'并且导致电子被俘获在俘获层上用于 逻辑状态'0'。 捕获层上的电荷捕获为存储的数据状态增加了额外的余量，防止了它们的降级，并且使单元非易失性。

    ENHANCED READ-WRITE METHODS FOR NEGATIVE DIFFERENTIAL RESISTANCE (NDR) BASED MEMORY DEVICE
    4.
    发明公开
    ENHANCED READ-WRITE METHODS FOR NEGATIVE DIFFERENTIAL RESISTANCE (NDR) BASED MEMORY DEVICE 审中-公开
    ADVANCED读写PROCESS FOR基于负阻力小信号的存储器模块（NDR）

    公开(公告)号：EP1518245A4

    公开(公告)日：2006-08-02

    申请号：EP03762013

    申请日：2003-06-25

    申请人： PROGRESSANT TECHNOLOGIES INC

    发明人： KING TSU-JAE

    IPC分类号： G11C11/00 ,  G11C11/39 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H01L21/28 ,  H01L29/788

    CPC分类号： G11C11/39 ,  G11C11/413

    摘要： An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

    ENHANCED READ-WRITE METHODS FOR NEGATIVE DIFFERENTIAL RESISTANCE (NDR) BASED MEMORY DEVICE
    6.
    发明公开
    ENHANCED READ-WRITE METHODS FOR NEGATIVE DIFFERENTIAL RESISTANCE (NDR) BASED MEMORY DEVICE 审中-公开
    ADVANCED读写PROCESS FOR基于负阻力小信号的存储器模块（NDR）

    公开(公告)号：EP1518245A2

    公开(公告)日：2005-03-30

    申请号：EP03762013.5

    申请日：2003-06-25

    申请人： Progressant Technologies Inc.

    发明人： KING, Tsu-Jae

    IPC分类号： G11C11/00

    CPC分类号： G11C11/39 ,  G11C11/413

    摘要： An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements (120, 130), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

    A CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
    8.
    发明公开
    A CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same 审中-公开
    CMOS-Prozess可兼容性abstimmbare负差异Widerstandanordnung und Betriebsverfahren

    公开(公告)号：EP1168456A3

    公开(公告)日：2003-08-27

    申请号：EP01105228.9

    申请日：2001-03-03

    申请人： Progressant Technologies Inc.

    发明人： Tsu-Jae King c/o Progressant Technologies Inc. ,  David K.YLiu c/o Progressant Technologies Inc.

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： B82Y10/00 ,  G11C5/142 ,  G11C11/39 ,  G11C16/04 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

    摘要： An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) (100) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals (145,155) of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.

    摘要翻译： 公开了在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。 对于固定栅极电压，在晶体管的漏极和源极端子之间流动的MISFET沟道电流首先随着漏极 - 源极电压增加到零伏特而增加。 一旦漏极到源极电压达到预定电平，电流随着漏极 - 源极电压的增加而减小。 在该操作区域中，由于漏极电流随着漏极电压的增加而减小，器件呈现负的差分电阻。 对应于负差分电阻开始的漏极 - 源极电压也是可调谐的。 此外，漏电流和负差分电阻可以通过调整栅极电压进行电子定制。 所得到的设备可以被并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

    A negative resistance device
    9.
    发明公开
    A negative resistance device 审中-公开
    负电阻器件

    公开(公告)号：EP1111620A3

    公开(公告)日：2003-01-08

    申请号：EP00650211.6

    申请日：2000-12-21

    申请人： National University of Ireland, Cork

    发明人： Duane, Russell ,  Mathewson, Alan ,  Concannon, Ann

    IPC分类号： G11C11/39

    CPC分类号： G11C11/39 ,  G11C5/142 ,  G11C2211/5614

    摘要： A negative resistance device (NRD) has a MOSFET-like structure, and is biased by:- shorting the gate and source together at a fixed applied potential and applying a different fixed potential to the drain, and sweeping the bulk potential towards the drain potential, causing the bulk current to exhibit a negative resistance characteristic. The NRD may be used in a memory circuit (10) in which a resistor (R) is connected between the bulk (2) and a fixed potential. Two States of the circuit at which the current through the resistor matches that through the bulk of the NRD are stable, providing for bistable memory operation.