公开(公告)号：EP1665286B1

公开(公告)日：2007-07-11

申请号：EP04769812.1

申请日：2004-08-17

申请人： Koninklijke Philips Electronics N.V.

发明人： BINK, Adrianus, J. ,  STRAVERS, Paul

IPC分类号： G11C29/00 ,  G06F12/08 ,  G06F12/10 ,  G06F11/14

CPC分类号： G11C29/76 ,  G06F12/0846 ,  G06F12/0864 ,  G11C29/88

摘要： An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

摘要翻译： 集成电路具有至少一个处理单元（TM），具有多个存储器模块的高速缓冲存储器（L2BANK）以及用于在所述多个存储器模块内执行无限制重映射的重映射装置（RM）。 因此，可以无限制地重新映射故障模块，以便通过提供故障模块的均匀分布来优化存储器模块的利用率。

公开(公告)号：EP1564755A2

公开(公告)日：2005-08-17

申请号：EP05250205.1

申请日：2005-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： Kim, Jin-hyuk ,  Chung, Hyun-mo ,  Myoung, Sung-ju ,  Cheong, Jae-wook ,  Park, Chan-ik ,  Chung, Tae-sun

IPC分类号： G11C29/00

CPC分类号： G11C29/76 ,  G06F12/0246

摘要： A data management apparatus and method used in a system using one or more flash memories, which can deal with defective blocks in each of the flash memories using different methods depending on how the system manages data stored in each of the flash memories. The data management apparatus includes a device driver (300), which controls the operation of one or more flash memories, and a controller (400), which transfers data stored in a defective block of one of the flash memories to a predetermined block in the flash memory (510,520).

摘要翻译： 一种在使用一个或多个闪速存储器的系统中使用的数据管理装置和方法，其可以使用不同的方法来处理每个闪速存储器中的缺陷块，这取决于系统如何管理存储在每个闪速存储器中的数据。 数据管理装置包括：控制一个或多个闪速存储器的操作的设备驱动器（300）;以及控制器（400），其将存储在其中一个闪速存储器的缺陷块中的数据传送到 闪存（510,520）。

公开(公告)号：EP1564747A1

公开(公告)日：2005-08-17

申请号：EP05250629.2

申请日：2005-02-04

申请人： SHARP KABUSHIKI KAISHA

发明人： Watanabe, Masahiko ,  Mori, Yasumichi

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C29/00

CPC分类号： G11C13/0028 ,  G11C13/0007 ,  G11C29/26 ,  G11C29/76 ,  G11C2029/2602 ,  G11C2213/31

摘要： A semiconductor memory device comprises at least one memory plane (4) in which a plurality of memory blocks (5) are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block (5) from the memory plane (4) and outputs block selection signals (BSEL0 to 3) for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals (BSEL0 to 3).

摘要翻译： 一种半导体存储器件包括至少一个存储器平面（4）在其上设置有存储块（5）的多个，并且一个块解码器电路，其用于选择所述存储块进行解码的块地址信号（5）从存储器平面（ 4）和输出块选择信号（BSEL0至3），用于选择存储块，以及将所有的块选择信号的选择状态，并在预定的测试模式输出它们，以及块选择信号反转电路用于反转 或非反转信号的块选择信号（至BSEL0 3）的水平。

公开(公告)号：EP1435625A1

公开(公告)日：2004-07-07

申请号：EP02425808.9

申请日：2002-12-30

申请人： STMicroelectronics S.r.l.

发明人： Khouri, Osama ,  Ravasio, Roberto ,  Micheloni, Rino ,  Campardo, Giovanni

IPC分类号： G11C29/00

CPC分类号： G11C29/76

摘要： A non volatile memory of the type comprising a predetermined number of sectors capable of ensuring the operation of the same even with a lower number of defective sectors than a predetermined limit.

摘要翻译： 这种类型的非易失性存储器包括能够确保即使具有比预定极限更少数量的缺陷扇区的扇区的预定数量的扇区。

公开(公告)号：EP1433183A1

公开(公告)日：2004-06-30

申请号：EP02800271.5

申请日：2002-09-27

申请人： TOKYO ELECTRON DEVICE LIMITED

发明人： YOSHII, Takeo,TOKYO ELECTRON DEVICE LIMITED ,  SHIMIZU, Masahiko,TOKYO ELECTRON DEVICE LIMITED

IPC分类号： G11C29/00

CPC分类号： G11C29/88 ,  G11C16/0483 ,  G11C16/102 ,  G11C29/76 ,  G11C29/883

摘要： Each of a plurality of storage devices (N-1 to N-n) has a plurality of memory blocks for storing data. A data writing apparatus obtains error information which represents good blocks which can store data correctly, from the plurality of storage devices (N-1 to N-n). The data writing apparatus determines a memory block in which data is to be written, in each of the plurality of storage devices (N-1 to N-n), based on the obtained error information. The data writing apparatus controls the plurality of storage devices (N-1 to N-n), and writes predetermined data in the determined memory blocks.

公开(公告)号：EP0809186B1

公开(公告)日：2003-03-26

申请号：EP97303385.5

申请日：1997-05-19

申请人： INFORMATION STORAGE DEVICES, INC.

发明人： Van Tran, Hieu ,  Blyth, Trevor

IPC分类号： G06F11/20

CPC分类号： G11C29/76 ,  G11C16/0441 ,  G11C16/08 ,  G11C29/789 ,  G11C29/80 ,  G11C29/812

公开(公告)号：EP1204122A2

公开(公告)日：2002-05-08

申请号：EP01308564.2

申请日：2001-10-08

申请人： Nokia Corporation

发明人： Kuiri, Tapio

IPC分类号： G11C29/00

CPC分类号： G11C29/76 ,  G11C11/22 ,  H01L27/118

摘要： A method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program being selected on the basis of the location of said one or more defects; and loading said program onto said integrated circuit.

摘要翻译： 在缺陷使用至少一个集成电路与的方法，所述方法包括确定开采的一个或多个缺陷的说位置集成电路的步骤; 选择节目将被存储在所述集成电路中，所述一个或多个缺陷的位置的基础上被选择的所述节目; 和加载所述程序到所述集成电路中。

公开(公告)号：EP0819276B1

公开(公告)日：2001-10-10

申请号：EP96902360.5

申请日：1996-02-14

申请人： IFA TECHNOLOGY INC.

发明人： DEAS, Alexander, Roger 8 Eskview Grove

IPC分类号： G06F11/20

CPC分类号： G11C29/76 ,  G11C29/781

摘要： A device for replacing defective storage locations with working storage locations comprises receiving means for receiving an incoming address for accessing a storage location, comparing means for comparing the incoming address with all of the addresses of known defective storage locations, and directing means for directing accesses to an alternative location when the incoming address matches one of the addresses of known defective storage locations. There is one alternative storage location and one comparing means for each known defective storage location. In this invention only a portion of the incoming address is used in the comparing means. In addition, each of the comparing means may use a different portion of the address for accessing a storage location.

公开(公告)号：EP0929036A2

公开(公告)日：1999-07-14

申请号：EP99300052.0

申请日：1999-01-05

申请人： INFORMATION STORAGE DEVICES, INC.

发明人： Tran, Hieu Van ,  Brennan, James, Jr.

IPC分类号： G06F11/20

CPC分类号： G11C29/76 ,  G11C11/5621 ,  G11C29/789 ,  G11C29/80

摘要： This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.

摘要翻译： 本发明提供了在一个存储阵列，其中电路在一个非易失性存储器芯片用于增加产率由于制造缺陷列冗余电路。 本发明包括一种方案以锁存并传送冗余信息，冗余逻辑电路，与列冗余阵列架构的冗余列驱动器，一个方案来编程和读取该列冗余存储单元，一个方案来复用的熔断器，并且 电路作为列冗余使能/禁止信号使用一个外的绑定地址。

公开(公告)号：EP0541288B1

公开(公告)日：1998-07-08

申请号：EP92309866.9

申请日：1992-10-28

申请人： Hsu, Fu-Chieh ,  Leung, Wingyu

发明人： Hsu, Fu-Chieh ,  Leung, Wingyu

IPC分类号： G06F11/20

CPC分类号： G11C29/832 ,  G06F11/2028 ,  G06F11/2051 ,  G06F12/0661 ,  G06F13/4077 ,  G11C29/006 ,  G11C29/48 ,  G11C29/76 ,  G11C29/808 ,  G11C29/88 ,  H01L22/22 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.