公开(公告)号：EP3042304A4

公开(公告)日：2017-06-07

申请号：EP13893029

申请日：2013-09-06

Applicant: INTEL CORP

Inventor： ANDERS MARK ,  CHEN GREGORY ,  KAUL HIMANSHU ,  KRISHNAMURTHY RAM ,  BORKAR SHEKHAR

IPC: G06F15/76 ,  G06F1/32 ,  G06F15/78 ,  H04L12/64 ,  H04L12/861 ,  H04L12/933 ,  H04L12/947

CPC classification number: H04L12/6418 ,  G06F15/7825 ,  H04L49/109 ,  H04L49/251 ,  H04L49/252 ,  H04L49/9042

Abstract: Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.

Abstract translation: 用于执行电路交换路由和技术和机制分组交换路由用于网络通信。 ，实施例中的路由器评估控制由所述路由器接收的分组的信息，评价检测是否所述分组包括用于在边带通信数据。 基于所述评估，路由器执行从路由器，模式包括第一模式，以将分组路由用于在网络中的边带数据的分组交换通信，所述多个模式中的一个。多个中进行选择。 因此模式的多元性包括第二模式配置的电路交换信道gemäß到分组。 在另一个中，路由器实施方式bestimmt用于在分层网络中路由分组，worin方向的确定性采矿的方向是基于所述路由器的在分层网络的层次结构的层次。

公开(公告)号：EP2377040A4

公开(公告)日：2017-06-07

申请号：EP09836574

申请日：2009-10-30

Applicant: MICROSOFT TECHNOLOGY LICENSING LLC

Inventor： ABDO NADIM Y ,  FILIZ ONUR ,  WOOD DANIEL N ,  MCMULLEN MAX ALAN

IPC: G06F15/76 ,  G06F9/06 ,  G06T9/00

CPC classification number: G06T9/001

公开(公告)号：EP3096234A1

公开(公告)日：2016-11-23

申请号：EP16170936.5

申请日：2016-05-23

Applicant: Goodrich Corporation

Inventor： RENCS, Erik V.

IPC: G06F15/76

Abstract: An integrated state vector management system for control systems includes a plurality of co-processors configured to generate and utilize state vector data. The integrated state vector management system further includes state vector module communicatively connected to each of the plurality of co-processors. The state vector module includes a state vector memory containing at least three memory buffers for storing three datasets of state vector data. The state vector module further includes a state vector memory control logic communicatively coupled to the state vector memory. The state vector control logic is configured to provide read and write control to the state vector memory. The state vector memory control logic includes at least a write pointer controller and a read pointer controller.

Abstract translation: 用于控制系统的集成状态向量管理系统包括被配置为生成和利用状态向量数据的多个协处理器。 集成状态向量管理系统还包括通信地连接到多个协处理器中的每一个的状态向量模块。 状态向量模块包括状态向量存储器，其包含用于存储状态向量数据的三个数据集的至少三个存储器缓冲器。 状态向量模块还包括通信地耦合到状态向量存储器的状态向量存储器控制逻辑。 状态向量控制逻辑被配置为向状态向量存储器提供读和写控制。 状态向量存储器控制逻辑至少包括写指针控制器和读指针控制器。

公开(公告)号：EP2351457B1

公开(公告)日：2016-10-05

申请号：EP09828010.0

申请日：2009-11-07

Applicant: Microsoft Technology Licensing, LLC

Inventor： BREWIS, Deon C. ,  MANDHANA, Taroon ,  TEH, Pehkeong

IPC: G06F15/76 ,  G06F9/44 ,  H04L12/24 ,  H04L29/06

CPC classification number: H04L41/0863 ,  H04L41/0806 ,  H04L41/0846 ,  H04L41/0893 ,  H04L69/18

公开(公告)号：EP2856331A1

公开(公告)日：2015-04-08

申请号：EP13798025.6

申请日：2013-05-29

Applicant: Cassy Holdings LLC

Inventor： Ross, Patrick D.

IPC: G06F15/76

CPC classification number: G06F7/58 ,  G06F7/588 ,  G06F21/00 ,  G06F21/62 ,  H04L9/0662 ,  H04L9/16 ,  H04L9/3236

Abstract: A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.

Abstract translation: 一种用于随机处理数据的系统，方法和设备。 存在在被配置为管理和控制数据的随机处理的处理器上操作的架构师模块，非确定性数据池模块被配置为提供不是从功能导出的非确定性值流，多个功能等效数据 处理模块，每个被配置为随机地处理由建筑师模块所要求的数据;配置为馈送希望进行随机处理的数据集的数据馈送;以及结构存储器模块，包括存储器存储设备，并且被配置为为建筑师提供足够的信息 模块来复制预定义的处理架构并记录利用的处理架构。

公开(公告)号：EP2721508A4

公开(公告)日：2015-04-01

申请号：EP12800997

申请日：2012-06-13

Applicant: MONTANA SYSTEMS INC

Inventor： BASHTEEN ASGHAR

IPC: G06F15/76 ,  G06F9/32 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F8/41 ,  G06F15/825 ,  G06F17/5009 ,  G06F2217/68

公开(公告)号：EP2351457A4

公开(公告)日：2014-07-09

申请号：EP09828010

申请日：2009-11-07

Applicant: MICROSOFT CORP

Inventor： BREWIS DEON C ,  MANDHANA TAROON ,  TEH PEHKEONG

IPC: G06F15/76 ,  G06F9/44 ,  H04L12/24 ,  H04L29/06

CPC classification number: H04L41/0863 ,  H04L41/0806 ,  H04L41/0846 ,  H04L41/0893 ,  H04L69/18

公开(公告)号：EP2729880A2

公开(公告)日：2014-05-14

申请号：EP12808115.5

申请日：2012-07-05

Applicant: Intel Corporation

Inventor： VARMA, Vishal V. ,  KOSHY, Kamal J.

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F9/328

Abstract: A system according to one embodiment includes a host central processing unit (CPU); a first storage medium configured to be in communication with the host CPU and to store information associated with at least one address; a second storage medium configured to be in communication with the host CPU, to store patch information associated with the at least one address of the first storage medium; and selection circuitry configured to, in response to a fetch instruction from the host CPU, select the patch information from the second storage medium if the fetch instruction contains a destination address that matches the at least one address associated with the patch information.

公开(公告)号：EP2689326A2

公开(公告)日：2014-01-29

申请号：EP12763717.1

申请日：2012-03-23

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F15/76

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3889 ,  G06F9/5027 ,  G06F12/0875 ,  G06F2209/507 ,  G06F2212/452 ,  Y02D10/22

Abstract: A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

Abstract translation: 一种用于使用用于处理器的多个存储器片段来执行指令的系统。 该系统包括用于接收输入指令序列的全局前端调度器，其中全局前端调度器将输入指令序列划分成多个指令代码块，并且生成描述代码块指令之间相互依赖关系的多个继承向量。 该系统还包括处理器的多个虚拟核心，其耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分区引擎的相应资源子集，其中通过使用 根据虚拟核心模式并根据各自的继承向量的可分割引擎。 多个存储器片段耦合到可分割引擎以提供数据存储。

公开(公告)号：EP2666112A1

公开(公告)日：2013-11-27

申请号：EP11856232.1

申请日：2011-09-20

Applicant: Algotochip Corporation

Inventor： KADIYALA, Suresh ,  NG, Pius ,  PANDURANGAN, Anand ,  PADMANABHAN, Satish ,  PLAYER, James

IPC: G06F17/50 ,  G06F15/76

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.