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    Schaltungsanordnung zum Erzeugen einer rauscharmen Hochfrequenzausgangsschwingung
    22.
    发明公开
    Schaltungsanordnung zum Erzeugen einer rauscharmen Hochfrequenzausgangsschwingung 失效
    Schaltungsanordnung zum Erzeugen einer rauscharmen Hochfrequenzausgangsschwingung。

    公开(公告)号：EP0026442A1

    公开(公告)日：1981-04-08

    申请号：EP80105730.8

    申请日：1980-09-24

    申请人： Rohde & Schwarz GmbH & Co. KG

    发明人： Frühauf, Tonio ,  Löffler, Heinrich ,  Richter, Josef

    IPC分类号： H03B1/04 ,  H03K21/00

    CPC分类号： H03B28/00

    摘要： Zum Erzeugen einer möglichst rauschamen Hochfrequenz-Ausgangsschwingung (A) mittels eines eine Ursprungsschwingung (0) höherer Frequenz erzeugenden Oszillators (1) und eines diese Ursprungsschwingung in der Frequenz herabteilenden Frequenzteilers (2) wird mit dem in der Frequenz herabgeteilten Ausgangssignal (U) des Frequenzteilers (2) ein elektronischer Schalter (3) gesteuert, der zwischen Oszillator (1) und Ausgang (12) angeordnet ist und mit dem unmittelbar aus der Ursprungsschwingung (0) des Oszillators (1) die in der Frequenz niedrigere Ausgangsschwingung (A) ausgeblendet wird.

    摘要翻译： 为了通过产生高频原始振荡（O）的振荡器（1）产生具有最低可能噪声的高频输出振荡（A），以及分频器（2）将该原始振荡频率降低， 用于分频器（2）的频率分频的输出信号（U）用于控制布置在振荡器（1）和输出（12）之间的电子开关（3），并且通过其输出振荡（A） 低频从振荡器（1）的原始振荡（O）直接提取。

    MEMORYLESS ACTIVE DEVICE WHICH TRAPS EVEN HARMONIC SIGNALS
    26.
    发明公开
    MEMORYLESS ACTIVE DEVICE WHICH TRAPS EVEN HARMONIC SIGNALS 审中-公开
    MEMORY LOSE有源器件用于检测谐波信号直

    公开(公告)号：EP3158642A1

    公开(公告)日：2017-04-26

    申请号：EP15809735.2

    申请日：2015-06-19

    申请人： Project FT, Inc.

    发明人： ARAM, Farbod

    IPC分类号： H03B5/12 ,  H03B1/04 ,  H03B5/00

    摘要： An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memoryless and traps even harmonic signals.

    FET BIAS CIRCUIT
    28.
    发明公开
    FET BIAS CIRCUIT 有权
    FET偏置电路

    公开(公告)号：EP1777812A4

    公开(公告)日：2007-08-29

    申请号：EP05745432

    申请日：2005-04-18

    申请人： YAN YUEJUN

    发明人： YAN YUEJUN

    IPC分类号： H03F1/30 ,  H03B1/04 ,  H03F3/16

    CPC分类号： H03F3/16 ,  H03F1/301 ,  H03F2200/18

    摘要： The invention discloses a FET (Field Effect Transistor) bias circuit, including current changing information circuit that has a power source resistance connected with the signal output end of this circuit, the other end of the resistance is connected with a reference voltage source, and the node between the resistance and the current changing information circuit acts as the output end providing the voltage changing information; and a voltage divider circuit connected with at least one voltage source, the voltage divider circuit is connected with the output end providing the voltage changing information; the current in a signal action FET is controlled by providing the voltage changing information at the output end to the voltage divider circuit and getting a dividing voltage from the voltage divider circuit to be a output end of the FET bias circuit. The bias circuit of the invention can make the static drain current of the signal action FET to remain constant, and reduce the deviation of the static drain current of the signal action FET of each chip in the whole wafer and its cost is low, its area is small, and it is easy to be integrated and fabricated.

    Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system
    30.
    发明公开
    Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system 有权
    在einem programmierbaren Phasenregelkreis中的Analoge Implementierung von Spreizspektrumfrequenzmodulation

    公开(公告)号：EP1359670A1

    公开(公告)日：2003-11-05

    申请号：EP03252802.8

    申请日：2003-05-02

    申请人： Altera Corporation

    发明人： Starr, Gregory W. ,  Chang, Wanli

    IPC分类号： H03L7/197 ,  H04B1/69 ,  H03C3/09 ,  H03B1/04 ,  H03L7/107

    CPC分类号： H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/18 ,  H03L7/1803 ,  H03M1/808 ,  H04B1/707

    摘要： A PLL circuit (100) is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator (112) coupled to the signal generator (110), where the spread spectrum modulator receives a control voltage (V CTRL ) as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage (V CTRL ). In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

    摘要翻译： 描述PLL电路（100）。 PLL电路包括：信号发生器; 以及耦合到信号发生器（110）的扩频调制器（112），其中扩频调制器接收控制电压（VCTRL）作为输入，并响应于控制电压向信号发生器提供扩频控制电压（ VCTRL）。 在一个实施例中，扩频调制器包括至少一个选择器，其中至少一个选择器选择对应于扩展模式的多个电压电平和扩频调制器的扩展百分比。