MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
    31.
    发明公开
    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG 失效
    MULTI-LAYER LINK CMOS器件与玻璃制成。

    公开(公告)号:EP0551306A1

    公开(公告)日:1993-07-21

    申请号:EP91916654.0

    申请日:1991-09-25

    申请人: MITEL CORPORATION

    发明人: OUELLET, Luc

    IPC分类号: H01L21 H01L27

    摘要: Procédé de fabrication d'une tranche de semi-conducteur, comprenant: le dépôt d'une première couche de matériau d'interconnexion sur un substrat; l'attaque du matériau d'interconnexion pour former des circuits d'interconnexion; la réalisation d'une première métallisation pour déposer une première couche diélectrique à basse température au-dessus des circuits d'interconnexion; l'aplanissement de la première couche diélectrique à basse température au moyen de verre filé quasi-inorganique ou inorganique par un procédé contraire à la gravure en retrait; le dépôt d'une deuxième couche diélectrique à basse température au-dessus du verre filé, la réalisation d'une désorption in-situ physique et chimique de vapeur d'eau dans une ambiance sèche à une température d'au moins 400 °C et non supérieure à 550 °C pendant une durée suffisante pour obtenir un taux de désorption négligeable, la température dépassant d'au moins 25 °C la température à laquelle la surface de la tranche sera exposée pendant une étape de métallisation ultérieure; la gravure de trous de transit à travers les couches de verre filé et diélectrique pour atteindre les circuits de la première couche d'interconnexion et la réalisation de l'étape de métallisation ultérieure pour déposer une deuxième couche d'interconnexion passant par les trous de transit vers les premiers circuits d'interconnexion tout en maintenant l'ambiance sèche. Les étapes ultérieures de gravure et de métallisation suivant l'étape de désorption sont effectuées sans re-exposer la tranche aux conditions ambiantes. Cette technique permet d'utiliser avec fiabilité des verres filés inorganiques et quasi-inorganiques dans un équipement de pulvérisation sans charge.

    CAPACITIVE MEASURING DEVICE WITH MOSFET
    32.
    发明授权
    CAPACITIVE MEASURING DEVICE WITH MOSFET 失效
    WITH A MOS FET电容性测量装置

    公开(公告)号:EP0776480B1

    公开(公告)日:2000-01-19

    申请号:EP95928908.3

    申请日:1995-08-21

    申请人: MITEL CORPORATION

    发明人: MANKU, Tajinder

    IPC分类号: G01R27/26

    CPC分类号: G01R27/2605

    摘要: A capacitance measuring device comprises a MOS transistor having a source, drain, and gate; a first capacitor C1 connected between the gate and the drain so that charge is coupled from said drain onto said gate; and a second capacitor C2 connected to a source of gate voltage VG and to the gate. One of the first and second capacitors has a known capacitance and the other has an unknown capacitance. A DC voltage is supplied between the source and drain to cause a saturation current to flow therebetween. The ratio delta VG/ delta Vd for the saturation current, where VG is the applied gate voltage, and Vd is the drain voltage, is measured and the unknown capacitance derived therefrom.

    SERIAL BIT RATE CONVERTER FOR A TDM SWITCHING MATRIX
    36.
    发明授权
    SERIAL BIT RATE CONVERTER FOR A TDM SWITCHING MATRIX 失效
    串行比特率转换用于时间复用VERMITTLUNGSKOPPLER

    公开(公告)号:EP0710426B1

    公开(公告)日:1997-10-01

    申请号:EP94921555.2

    申请日:1994-07-13

    申请人: MITEL CORPORATION

    IPC分类号: H04Q11/08

    CPC分类号: H04J3/047 H04Q11/08

    摘要: A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The output side of the switching matrix can be similarly configured.

    OPTIMIZATION CIRCUIT
    37.
    发明授权
    OPTIMIZATION CIRCUIT 失效
    最优化电路

    公开(公告)号:EP0708939B1

    公开(公告)日:1997-06-04

    申请号:EP94921556.0

    申请日:1994-07-13

    申请人: MITEL CORPORATION

    IPC分类号: G05F3/24

    摘要: A method of improving the performance of an active semiconductor device with a voltage-controllable channel length, comprises providing a matched reference component having similar operating characteristics to the active semiconductor device, continually monitoring the breakdown voltage of the matched reference component, and maintaining the operating voltage of the active semiconductor device to lie just below the measured breakdown voltage of the matched reference component. In this way, the performance of the active component can be optimized.

    OFF-HOOK TELEPHONE WITH TEMPORARY PARK FEATURE
    38.
    发明授权
    OFF-HOOK TELEPHONE WITH TEMPORARY PARK FEATURE 失效
    在环路条件的电话机时间停车设备

    公开(公告)号:EP0599931B1

    公开(公告)日:1997-05-14

    申请号:EP92917629.5

    申请日:1992-08-21

    申请人: MITEL CORPORATION

    发明人: MILC, Thomas, A.

    IPC分类号: H04M1/06

    CPC分类号: H04M1/06

    摘要: A telephone apparatus comprises a base and a handset. An inclined cradle is provided on the base for receiving the handset and is shaped such that a handset placed thereon normally falls naturally into a fully seated position. A switch means responsive to the presence or absence of the handset in the cradle places the apparatus in an 'on-hook' or 'off-hook' condition respectively. A co-operating arrangement respectively on the handset and the base permit said handset to be temporarily retained in a partially seated position on the cradle without activating the switch means so as to permit the handset to be parked temporarily on the cradle without placing the apparatus in the 'on-hook' condition.

    SIGNAL PROCESSING CIRCUIT
    39.
    发明公开
    SIGNAL PROCESSING CIRCUIT 失效
    信号处理电路

    公开(公告)号:EP0769225A1

    公开(公告)日:1997-04-23

    申请号:EP95923162.0

    申请日:1995-07-06

    申请人: MITEL CORPORATION

    IPC分类号: H03M7 H04B14

    CPC分类号: H03M7/3046

    摘要: A circuit for applying a predetermined algorithm to an input signal, comprises an input for receiving the input signal, a signal processing device for processing the input signal in accordance with the predetermined algorithm, and a device for outputting the processed signal, the signal processing device comprising distributed bit-serial logic circuits to implement the predetermined algorithm.

    OPTIMIZATION CIRCUIT
    40.
    发明公开
    OPTIMIZATION CIRCUIT 失效
    OPTIMIERUNGSCHALTUNG

    公开(公告)号:EP0708939A1

    公开(公告)日:1996-05-01

    申请号:EP94921556.0

    申请日:1994-07-13

    申请人: MITEL CORPORATION

    IPC分类号: G05F3 G05F1 G11C11 H03K17 H03K19

    摘要: A method of improving the performance of an active semiconductor device with a voltage-controllable channel length, comprises providing a matched reference component having similar operating characteristics to the active semiconductor device, continually monitoring the breakdown voltage of the matched reference component, and maintaining the operating voltage of the active semiconductor device to lie just below the measured breakdown voltage of the matched reference component. In this way, the performance of the active component can be optimized.