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13 条记录 (耗时 0.012 秒)

    PREVENTING OF VIA POISONING BY GLOW DISCHARGE INDUCED DESORPTION
    3.
    发明授权
    PREVENTING OF VIA POISONING BY GLOW DISCHARGE INDUCED DESORPTION 失效
    保护单元通过平衡由辉光放电诱导解吸手段。

    公开(公告)号：EP0563113B1

    公开(公告)日：1995-03-01

    申请号：EP92900971.0

    申请日：1991-12-18

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc

    IPC分类号： H01L21/3105 ,  H01L21/3205

    CPC分类号： H01L21/31058

    摘要： A method of fabricating multilevel semiconductor wafers including a spin-on glass planarization layer is described. Prior to sputtering of the interconnect layer and after application of the spin-on glass layer, the wafer is exposed to an intense glow discharge in such a way that it is bombarded in at least a partial vacuum with ions and/or electrons and/or photons while at a temperature that is between 400 °C and 550 °C and that is at least 25 °C higher than the temperature to which the wafer is to be subjected during the subsequent sputtering step. In this way undesirable molecules can be desorbed from the spin-on glass layer so that they do not interfere with the subsequent sputtering step.

    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES
    4.
    发明授权
    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES 失效
    钝化FOR半导体布置高性能

    公开(公告)号：EP0598795B1

    公开(公告)日：1998-06-03

    申请号：EP92917204.7

    申请日：1992-08-10

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc

    IPC分类号： H01L23/29 ,  H01L23/00 ,  H01L21/312 ,  H01L23/485

    CPC分类号： H01L21/02142 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/3121 ,  H01L23/296 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

    摘要： PCT No. PCT/CA92/00346 Sec. 371 Date Feb. 23, 1994 Sec. 102(e) Date Feb. 23, 1994 PCT Filed Aug. 10, 1992 PCT Pub. No. WO93/04501 PCT Pub. Date Mar. 4, 1993A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.

    STABILIZATION OF THE INTERFACE BETWEEN TiN AND A1 ALLOYS
    5.
    发明公开
    STABILIZATION OF THE INTERFACE BETWEEN TiN AND A1 ALLOYS 失效
    边界之间的锡和铝合金镇定

    公开(公告)号：EP0902968A1

    公开(公告)日：1999-03-24

    申请号：EP97945682.0

    申请日：1997-11-26

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc ,  TREMBLAY, Yves ,  GENDRON, Luc

    IPC分类号： H01L21

    CPC分类号： H01L21/76846 ,  H01L21/76856

    摘要： A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.

    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES
    6.
    发明公开
    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES 失效
    钝化FOR半导体布置高性能。

    公开(公告)号：EP0598795A1

    公开(公告)日：1994-06-01

    申请号：EP92917204.0

    申请日：1992-08-10

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc

    IPC分类号： H01L21 ,  H01L23

    CPC分类号： H01L21/02142 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/3121 ,  H01L23/296 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

    摘要： PCT No. PCT/CA92/00346 Sec. 371 Date Feb. 23, 1994 Sec. 102(e) Date Feb. 23, 1994 PCT Filed Aug. 10, 1992 PCT Pub. No. WO93/04501 PCT Pub. Date Mar. 4, 1993A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.

    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
    7.
    发明公开
    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG 失效
    MULTI-LAYER LINK CMOS器件与玻璃制成。

    公开(公告)号：EP0551306A1

    公开(公告)日：1993-07-21

    申请号：EP91916654.0

    申请日：1991-09-25

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc

    IPC分类号： H01L21 ,  H01L27

    CPC分类号： H01L21/02337 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76828 ,  Y10S438/974

    摘要： Procédé de fabrication d'une tranche de semi-conducteur, comprenant: le dépôt d'une première couche de matériau d'interconnexion sur un substrat; l'attaque du matériau d'interconnexion pour former des circuits d'interconnexion; la réalisation d'une première métallisation pour déposer une première couche diélectrique à basse température au-dessus des circuits d'interconnexion; l'aplanissement de la première couche diélectrique à basse température au moyen de verre filé quasi-inorganique ou inorganique par un procédé contraire à la gravure en retrait; le dépôt d'une deuxième couche diélectrique à basse température au-dessus du verre filé, la réalisation d'une désorption in-situ physique et chimique de vapeur d'eau dans une ambiance sèche à une température d'au moins 400 °C et non supérieure à 550 °C pendant une durée suffisante pour obtenir un taux de désorption négligeable, la température dépassant d'au moins 25 °C la température à laquelle la surface de la tranche sera exposée pendant une étape de métallisation ultérieure; la gravure de trous de transit à travers les couches de verre filé et diélectrique pour atteindre les circuits de la première couche d'interconnexion et la réalisation de l'étape de métallisation ultérieure pour déposer une deuxième couche d'interconnexion passant par les trous de transit vers les premiers circuits d'interconnexion tout en maintenant l'ambiance sèche. Les étapes ultérieures de gravure et de métallisation suivant l'étape de désorption sont effectuées sans re-exposer la tranche aux conditions ambiantes. Cette technique permet d'utiliser avec fiabilité des verres filés inorganiques et quasi-inorganiques dans un équipement de pulvérisation sans charge.

    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
    10.
    发明授权
    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG 失效
    具有SOG的多电平互连CMOS器件

    公开(公告)号：EP0551306B1

    公开(公告)日：1995-12-13

    申请号：EP91916654.6

    申请日：1991-09-25

    申请人： MITEL CORPORATION

    发明人： OUELLET, Luc

    IPC分类号： H01L21/768 ,  H01L21/314 ,  H01L21/312

    CPC分类号： H01L21/02337 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76828 ,  Y10S438/974

    摘要： A method of manufacturing a semiconductor wafer, comprises depositing a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, performing a first metallization to deposit a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, performing an in-situ desorption of physically and chemically water vapour in a dry environment at a temperature of at least 400 °C and not more than 550 °C for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25 °C the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks while maintaining the dry environment. The subsequent etching and metallization steps after the desorption step are performed without re-exposure of the wafer to ambient conditions. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.

    摘要翻译： 一种制造半导体晶片的方法，包括在衬底上沉积第一层互连材料，蚀刻互连材料以形成互连线路，执行第一金属化以在互连线路上沉积第一低温介电层，平坦化第一低 通过非深腐蚀工艺在准无机或无机旋涂玻璃上沉积高温介电层，在旋涂玻璃上沉积第二低温介电层，在干燥环境中进行物理和化学水蒸汽的原位解吸 在至少400℃且不超过550℃的温度下持续足以获得可忽略不计的解吸速率的时间，温度超过晶片表面将暴露于其中的温度至少25℃ 随后的金属化步骤，蚀刻穿过介电层和旋涂玻璃层的通孔以到达第一互连层的轨道， 以及执行随后的金属化步骤以将延伸穿过所述通孔的第二互连层沉积到所述第一互连迹线，同时保持所述干燥环境。 在解吸步骤之后进行后续的蚀刻和金属化步骤，而不会将晶片重新暴露在环境条件下。 该技术允许在非间歇式溅射设备中可靠地使用无机或准无机旋涂玻璃。