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36 条记录 (耗时 0.016 秒)

    High efficiency electronic circuit for generating and regulating a supply voltage
    31.
    发明公开
    High efficiency electronic circuit for generating and regulating a supply voltage 有权
    用于产生和调节电源电压的高效率电子电路

    公开(公告)号：EP1184962A1

    公开(公告)日：2002-03-06

    申请号：EP00830586.4

    申请日：2000-08-22

    申请人： STMicroelectronics S.r.l. ,  TECDIS S.p.A.

    发明人： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

    IPC分类号： H02M3/07

    CPC分类号： H02M3/073

    摘要： This invention relates to a high-efficiency electronic circuit (1) for generating and regulating a supply voltage (Vout), comprising a charge-pump voltage multiplier (2) which is associated with an oscillator (3) and has an output connected to a voltage regulator (4) in order to ultimately output said supply voltage (Vout). Advantageously, the circuit comprises a first hysteresis comparator (5) having as inputs the regulator (4) output and the multiplier (2) output, and comprises a second hysteresis comparator (6) having as inputs a reference potential (Vrif) and a partition (K) of the voltage (Vout) presented on the regulator (4) output.
    The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator (3) through a logic circuit (7) to modulate the oscillator (3) operation.

    摘要翻译： 本发明涉及一种用于产生和调节的供给电压（Vout），其包括一个电荷泵电压倍增器的高效率电子电路（1）（2）所有其与在振荡器相关联的（3），并且具有对连接到输出 为了电压调节器（4），以最终所述输出电源电压（Vout）。 有利的是，该电路包括一个第一磁滞比较器（5），其具有作为输入的调节器（4）输出和乘法器（2）输出，和包括第二迟滞比较器（6），其具有作为输入的基准电势（Vrif）和分区 的电压的（K）（VOUT）呈现在调节器（4）输出。 比较器在结构上和功能上独立的海誓山盟，并且它们的输出通过一个逻辑电路（7）来调制所述振荡器（3）操作耦合到所述振荡器（3）。

    Turn off circuit for an LDMOS in presence of a reverse current
    35.
    发明公开
    Turn off circuit for an LDMOS in presence of a reverse current 失效
    Schaltung zum Abschalten eines LDMOS晶体管在Anwesenheit von einem Gegenstrom

    公开(公告)号：EP0887933A1

    公开(公告)日：1998-12-30

    申请号：EP97830298.2

    申请日：1997-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

    IPC分类号： H03K17/06

    CPC分类号： H03K17/063 ,  H03K2217/0018

    摘要： A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance, via a bootstrap capacitor (Cp) charged by a diode at the supply voltage (Vs) of the circuit, by an inverter (IO1) driven by a logic control circuit in function of a Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase wherein the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, uses a first zener diode (Z1) to charge the bootstrap (Cp) and the source of the (LD) transistor is connected to the supply node (Vs) through a second zener diode (Z2).

    摘要翻译： 一种用于通过用作源极跟随器的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，其通过经由自举电容器（Cp）的电容器（Cp）来模拟电容器的高电压充电二极管 通过由低栅极驱动信号的功能的逻辑控制电路驱动的反相器（IO1）和在阶段期间有效的第二逻辑信号（UVLOb）的电路的电源电压（Vs）处的二极管， 电源电压（Vs）低于集成电路的最小接通电压，使用第一齐纳二极管（Z1）对自举（Cp）充电，并且（LD）晶体管的源极连接到电源节点 Vs）通过第二齐纳二极管（Z2）。

    Control of the body voltage of a high voltage LDMOS
    36.
    发明公开
    Control of the body voltage of a high voltage LDMOS 失效
    Steuerung derKörperspannungeines Hochspannungs-LDMOS晶体管

    公开(公告)号：EP0887932A1

    公开(公告)日：1998-12-30

    申请号：EP97830297.4

    申请日：1997-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Genova, Angelo ,  Tarantola, Mario ,  Cantone, Giuseppe ,  Gariboldi, Roberto

    IPC分类号： H03K17/06

    CPC分类号： H03K17/063 ,  H03K2217/0018

    摘要： A circuit for charging a capacitance (C) by mens of an LDMOS (LD) integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance and comprising a circuital device to avert the switch-on parasitic PNP transistors of the LDMOS structure during transient states, composed of a number n of junctions (d1, D2, .. , Dn) directly biased between a source node (S) and a body node (VB) of the LDMOS transistor, at least a current generator (I), referred to the potential of a ground node of the circuit, at least a switch (SW1) between said source node (S) and the first junction (D1) of said chain of directly biased junctions and a limiting resistance (R1) connected between said body node and said current generator (I) referred to ground in which the (SW1) switch is open during a charging phase of the capacitance (C) and is closed when the charging voltage of the capacitance goes over a preestablished threshold by a control signal, further comprises

    switching means (Sd1, Sd2, Sd3, Sd4) controlled by a logic signal (UVLO), active during the phase in which the supply voltage (Vs) of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging said body node (VB) with a current whose maximum value is limited to a preestablished value.

    摘要翻译： 一种用于以模拟高电压充电二极管的方式控制的LDMOS（LD）集成晶体管的电容（C）进行充电的电路，并且包括电路装置以反转LDMOS的接通的寄生PNP晶体管 由在直接偏置在LDMOS晶体管的源极节点（S）和体节点（VB）之间的n个结（d1，D2，...，Dn）组成的至少一个电流发生器（I ）指的是电路的接地节点的电位，至少在所述源极节点（S）和所述直接偏置接合链的第一结（D1）之间的开关（SW1）和连接的限制电阻（R1） 在所述体节点和所述电流发生器（I）之间称为接地，其中（SW1）开关在电容（C）的充电阶段期间断开，并且当电容的充电电压超过预先建立的阈值时闭合 控制信号还包括切换 由逻辑信号（UVLO）控制的装置（Sd1，Sd2，Sd3，Sd4）在集成电路的电源电压（Vs）低于同一集成电路的最小接通电压的相位中有效， 用于用最大值被限制为预定值的电流对所述身体节点（VB）进行充电。