公开(公告)号：EP0212545A2

公开(公告)日：1987-03-04

申请号：EP86111132.6

申请日：1986-08-12

申请人： FUJITSU LIMITED

发明人： Nakano, Masao ,  Takemae, Yoshihiro

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1033

摘要： In a semiconductor memory device having a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks; data bus lines are provided separately to each of the first and second cell blocks; sense amplifiers are provided separately to each of data bus lines; a column decoder for connecting between bit lines is provided in the memory cell array and corresponding data bus lines based on address signals and gate signals in selection state; a switching circuit is provided for switching between sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and for connecting these sense amplifiers to output buffers; and a clock signal generating circuit is provided for generating the gate signals, and the gate signals are generated by such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of the column address strobe signal in the nibble mode.

摘要翻译： 在具有半字模式功能的半导体存储器件中，存储单元阵列被分成两组第一和第二单元块; 数据总线分别提供给第一和第二单元块中的每一个; 读出放大器分别提供给每条数据总线; 用于连接位线的列解码器基于选择状态下的地址信号和门信号提供在存储单元阵列和对应的数据总线中; 提供了一种开关电路，用于切换属于第一单元块的读出放大器和属于第二单元块的读出放大器，并将这些读出放大器连接到输出缓冲器; 并且提供时钟信号发生电路用于产生栅极信号，并且通过这样一种方式生成栅极信号，使得每个栅极信号响应于列地址选通信号的前沿而升高并且被允许响应于 列地址选通信号的后沿是半字节模式。

公开(公告)号：EP0202873A2

公开(公告)日：1986-11-26

申请号：EP86303719.8

申请日：1986-05-15

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro

IPC分类号： G06F11/20 ,  G06F11/10

CPC分类号： G11C29/70 ,  G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device is provided which comprises a main memory cell array (MCA) including a plurality of rows of cell arrays each row corresponding to a two-dimensional virtual matrix configuration, and a redundancy memory cell array (RCA') including a plurality of rows of redundancy memory cells each row corresponding to one horizontal or vertical group of memory cells of the virtual matrix configuration. When a selected memory cell is a predetermined defective cell, a row of memory cells including such a defective cell is replaced with the redundancy memory cell array, thereby correcting a hard error. Also, when such a defective cell is accessed by an error checking and correcting (ECC) circuit of a horizontal and vertical parity checking type, a horizontal or vertical group of memory cells including the selected memory cell is replaced with the corresponding row of the redundancy memory cell array, thereby correcting a soft error and a hard error other than the predetermined hard error.

公开(公告)号：EP0201185A2

公开(公告)日：1986-11-12

申请号：EP86302306.5

申请日：1986-03-27

申请人： FUJITSU LIMITED

发明人： Sato, Kimiaki ,  Takemae, Yoshihiro ,  Nakano, Masao ,  Kodama, Nobumi Fujitsu Dai-go Nakahara-ryo

IPC分类号： G11C8/00 ,  G11C11/40

CPC分类号： G11C8/10 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/12

摘要： @ In a semiconductor memory device, a decoder circuit (1) is located between first (3) and second (5) memory cell arrays. A sequence of driver circuits (121,122...) in the decoder circuit (1) provides driver circuits common to the first and second memory cell arrays. An output terminal (1211 a,1211b,1221a,...) of each driver circuit is connected directly to a data input/output portion (2) for the first memory cell array (3) and connected to another data input/output portion (4) for the second memory cell array (5) via wirings (141 a, 141 b, 142a, ...) traversing the decoder circuit (1 ).

公开(公告)号：EP0037239B1

公开(公告)日：1986-10-15

申请号：EP81301269.7

申请日：1981-03-25

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro

IPC分类号： G11C7/00 ,  G11C11/24

CPC分类号： G11C5/066 ,  G11C11/4093

公开(公告)号：EP0174845A2

公开(公告)日：1986-03-19

申请号：EP85306464.0

申请日：1985-09-11

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro

IPC分类号： G11C8/00

CPC分类号： G11C7/1036 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

摘要： The semiconductor memory device can continuously read or store a plurality of data therefrom or therein. The semiconductor memory device includes a memory unit having a plurality of memory cells (3,4), the memory cells being arranged in a matrix having rows and columns, and a reading storing circuit. The reading storing circuit can read or store data from or into the memory cell at an address corresponding to an address signal received therein in response to the reception of first and second control signals, respectively. The reading storing circuit also can consecutively read or store data from or into the memory cell at another address subsequent to the address read or stored at the last time in response to the reception of the second control signal. Such a device can therefore have improved access time for continuous accessing of a plurality of data.

摘要翻译： 半导体存储器件可以从其中或其中连续读取或存储多个数据。 半导体存储器件包括具有多个存储器单元（3,4）的存储器单元以及读取存储电路，存储器单元被排列成具有行和列的矩阵。 读取存储电路可以分别响应于第一和第二控制信号的接收，在与其中接收到的地址信号相对应的地址处从或向存储器单元读取或存储数据。 读取存储电路还可以在地址读取之后的另一个地址处连续读取或存储来自存储器单元的数据或将数据存储在存储器单元中，或者响应于第二控制信号的接收在最后一次存储。 这样的设备因此可以具有用于连续访问多个数据的改进的访问时间。

公开(公告)号：EP0145606A3

公开(公告)日：1986-01-29

申请号：EP84402560

申请日：1984-12-12

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro

IPC分类号： H01L27/10

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： @ A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor (10) and a capacitor (11). The capacitor (11) is a so-called groove-type capacitor and has a conductive layer (18) formed on an insulation film (17) attached to the inside surface of a groove (16) formed on a semiconductor substrate (12). The conductive layer (18) is electrically coupled to the source (14) of the transfer gate transistor (10). The capacitance of the capacitor (11) is formed between the conductive layer (18) and a second conductive layer (20) formed on the conductive layer (18) via an insulation film (19), and/or between the conductive layer (18) and the semiconductor substrate (12).

摘要翻译： 半导体存储装置，例如MOS动态RAM装置，具有包括传输门晶体管（10）和电容器（11）的存储单元。 电容器（11）是所谓的沟槽型电容器，并具有形成在绝缘膜（17）上的导电层（18），绝缘膜（17）连接到形成在半导体衬底（12）上的沟槽（16）的内表面。 导电层（18）电耦合到传输门晶体管（10）的源极（14）。 电容器（11）的电容经由绝缘膜（19）形成在导电层（18）和在导电层（18）上形成的第二导电层（20）之间，和/或在导电层 ）和半导体衬底（12）。

公开(公告)号：EP0080935A3

公开(公告)日：1985-12-18

申请号：EP82402138

申请日：1982-11-24

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Ohira, Tsuyoshi Kurashi-no-Kyoshitsu 102 ,  Enomoto, Seiji

IPC分类号： G11C11/24

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5004

摘要： A dynamic semiconductor memory device provides a selected real cell which is connected to one of a pair of bit lines connected to a sense amplifier and a dummy cell which is connected to the other bit line so as to perform the read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation, or a write circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the read cell is tested, an optional power source can be applied from the test power source pad instead of from a normal power source.

公开(公告)号：EP0163580A2

公开(公告)日：1985-12-04

申请号：EP85401065.9

申请日：1985-05-30

申请人： FUJITSU LIMITED

发明人： Nakano, Masao ,  Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Sato, Kimiaki ,  Tsuge, Norihisa

IPC分类号： G06F11/20

CPC分类号： G11C29/835

摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit (24) for detecting coincidence between data read from the memory unit (21) and a received input address (Ao, An). Data produced from the comparison by the comparison unit is delivered through an external connection terminal (7).

公开(公告)号：EP0145606A2

公开(公告)日：1985-06-19

申请号：EP84402560.1

申请日：1984-12-12

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro

IPC分类号： H01L27/10

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： @ A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor (10) and a capacitor (11). The capacitor (11) is a so-called groove-type capacitor and has a conductive layer (18) formed on an insulation film (17) attached to the inside surface of a groove (16) formed on a semiconductor substrate (12). The conductive layer (18) is electrically coupled to the source (14) of the transfer gate transistor (10). The capacitance of the capacitor (11) is formed between the conductive layer (18) and a second conductive layer (20) formed on the conductive layer (18) via an insulation film (19), and/or between the conductive layer (18) and the semiconductor substrate (12).

公开(公告)号：EP0145595A2

公开(公告)日：1985-06-19

申请号：EP84402512.2

申请日：1984-12-06

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Nakano, Masao ,  Sato, Kimiaki

IPC分类号： G11C17/00 ,  H01L23/52 ,  G06F11/20

CPC分类号： G11C29/785 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses (F,) for constituting the ROM, pads (PB) for supplying a melting current to the fuses, and PN junctions (D 1 ) each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction (D i ), the fuse (F 1 ), and the pad (PB) so that the PN junction (D i ) is forward biased, and thereby, supplying a large current to the fuse.