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    Method and system for high-speed virtual-to-physical address translation and cache tag matching
    31.
    发明公开
    Method and system for high-speed virtual-to-physical address translation and cache tag matching 失效
    用于高速虚拟到物理地址转换和高速缓存标签匹配的方法和系统

    公开(公告)号：EP0549321A3

    公开(公告)日：1993-09-08

    申请号：EP92311689.1

    申请日：1992-12-22

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Bosshart, Patrick W.

    IPC分类号： G06F12/10 ,  G06F12/08

    CPC分类号： G06F12/1054

    摘要： A circuit (100) for high-speed virtual-to-physical address translation and cache tag matching comprises a set-associative memory management unit (112) for producing a first predetermined number, N, of candidate physical address signals (132 and 134), and N candidate address hit signals (150 and 152). A set-associative cache (114) produces a second predetermined number M of address tags (168 and 170) and N-by-M array (M00, M01, M10 and M11) of comparison circuits compare the candidate physical addresses (132 and 134) with address tags (168 and 170) gating by the N address hit signals to generate cache hit signals.

    Hierarchical architecture for determining the least recently used cache memory
    33.
    发明公开
    Hierarchical architecture for determining the least recently used cache memory 失效
    分层结构确定最近最少使用的缓存。

    公开(公告)号：EP0173556A2

    公开(公告)日：1986-03-05

    申请号：EP85306082.0

    申请日：1985-08-28

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Bosshart, Patrick W.

    IPC分类号： G06F12/12 ,  G06F12/08

    CPC分类号： G06F12/126 ,  B23K26/08 ,  G06F12/0864 ,  G06F12/125 ,  G06F2212/1032

    摘要： A cache memory system includes a set of associative data memories (108), (110), (112) and (114) with associated tag memories (116), (118), (120) and (122). The output of the Tag Memories are input to comparator circuits (144), (146), (148) and (150) to compare the most significant bits therein with the most significant bits on the address bus (124). Each of the tag memories (116)-(122) is directly addressable by either a virtual or a physical address with the most significant bits of each address contained in each tag memory. An LRU controller (172) controls the selection of the data memories (108)-(114) for writing data therein to determine which of the memories is the least recently used one. The LRU controller (172) is interfaced with an RLU memory (176) for storage of LRU data therein. In addition, fault information is stored in a fault memory (184) to prevent the LRU controller (172) from selecting a faulty memory location for writing of data thereto.

    摘要翻译： 高速缓冲存储器系统包括：（108），（110）相关联的标签的存储器（116），（118），（120）和（122）的一组相联的数据存储器，（112）和（114）。 日存储器的输出被输入到比较器电路（144）（146）（148）和（150）的最显著位与其中的地址总线（124）上的最显著位进行比较。 每个标记存储器（116） - （122）直接通过无论是虚拟或物理地址与每个地址的包含在每个标记存储器中的最显著位寻址。 一个LRU控制器（172）控制的数据存储器（108）的选择 - 用于在其中写入数据，以确定哪一个矿井的记忆是最近最少使用的一个（114）。 该LRU控制器（172）在RLU存储器（176），用于数据LRU在其中存储与接口。 此外，故障信息被存储在一个故障存储器（184），以防止选择一个故障memorelocation用于向其写入数据的LRU控制器（172）。

    Processor with improved branch efficiency
    36.
    发明公开
    Processor with improved branch efficiency 有权
    处理器具有增强效果的分支

    公开(公告)号：EP1117032A3

    公开(公告)日：2005-08-17

    申请号：EP01100846.3

    申请日：2001-01-15

    申请人： Texas Instruments Incorporated

    发明人： Bosshart, Patrick W.

    IPC分类号： G06F9/38

    CPC分类号： G06F9/325 ,  G06F9/30072 ,  G06F9/3853

    摘要： A processor (50) having a changeable architected state. The processor includes an instruction memory (52) for storing instructions. The processor also includes an instruction pipeline, where an instruction which passes entirely through the pipeline alters the architected state. Further, the pipeline comprises circuitry for fetching (58aa) instructions from the instruction memory into the pipeline. The processor also includes circuitry for storing an annul code (46) corresponding to instructions in the pipeline. Finally, the processor includes circuitry for preventing (FU 1 through FU 8 ) one or more selected instructions in the group from altering the architected state in response to the annul code.

    Method and system for generating charge sharing test vectors
    37.
    发明公开
    Method and system for generating charge sharing test vectors 有权
    方法和系统，用于产生电荷共享测试矢量

    公开(公告)号：EP1122547A3

    公开(公告)日：2003-08-13

    申请号：EP01200354.7

    申请日：2001-01-31

    申请人： Texas Instruments Incorporated

    发明人： Heraçu, Keerthinarayan P. ,  Bosshart, Patrick W.

    IPC分类号： G01R31/3183

    CPC分类号： G01R31/3183

    摘要： A method for generating charge sharing test vectors for a circuit is provided that includes providing an automatic test pattern generator operable to generate a first test vector (120) and a second test vector (122). The method further includes providing a test model (98) including a logic cell of a circuit and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method next provides for selecting an output of the discharge AND gate (104) as a target for a falling transition fault test vector generation by the automatic test pattern generator (124). The method next provides for generating a first test vector (120) for the test model (98) using the automatic test pattern generator (124) where the first test vector (120) provides an input pattern to discharge nodes of the logic cell. In addition, the discharge AND gate (102) evaluates to a logic level 1 for the first test vector (120). The method next provides for generating a second test vector (122) for the test model (98) using the automatic test pattern generator (124) where the second test vector (122) provides an input pattern to evoke the worst charge sharing behavior for the logic cell. In addition, the charge sharing AND gate (104) evaluates to a logic level 1 for the second test vector (122).

    Processor with improved branch efficiency
    39.
    发明公开
    Processor with improved branch efficiency 有权
    Prozessor mit verbesserter Verzweigungswirkung

    公开(公告)号：EP1117032A2

    公开(公告)日：2001-07-18

    申请号：EP01100846.3

    申请日：2001-01-15

    申请人： Texas Instruments Incorporated

    发明人： Bosshart, Patrick W.

    IPC分类号： G06F9/38

    CPC分类号： G06F9/325 ,  G06F9/30072 ,  G06F9/3853

    摘要： A processor (50) having a changeable architected state. The processor includes an instruction memory (52) for storing instructions. The processor also includes an instruction pipeline, where an instruction which passes entirely through the pipeline alters the architected state. Further, the pipeline comprises circuitry for fetching (58aa) instructions from the instruction memory into the pipeline. The processor also includes circuitry for storing an annul code (46) corresponding to instructions in the pipeline. Finally, the processor includes circuitry for preventing (FU 1 through FU 8 ) one or more selected instructions in the group from altering the architected state in response to the annul code.

    摘要翻译： 具有可改变的架构状态的处理器（50）。 处理器包括用于存储指令的指令存储器（52）。 处理器还包括指令流水线，其中完全通过管道的指令改变了架构状态。 此外，流水线包括用于从指令存储器读取（58aa）指令到管线中的电路。 处理器还包括用于存储对应于管线中的指令的废止码（46）的电路。 最后，处理器包括用于防止（FU1至FU8）组中的一个或多个所选择的指令响应于废止代码改变架构状态的电路。

    Hybrid data and clock precharging techniques in domino logic circuits minimizes charge sharing during evaluation
    40.
    发明公开
    Hybrid data and clock precharging techniques in domino logic circuits minimizes charge sharing during evaluation 有权
    混合传票技术在多米诺逻辑电路的数据和时钟，这在评价期间减少的电荷分布

    公开(公告)号：EP0954101A3

    公开(公告)日：2000-06-14

    申请号：EP99201372.2

    申请日：1999-04-29

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Srivastava, Pranjal ,  Bosshart, Patrick W. ,  Ko, Uming

    IPC分类号： H03K19/096 ,  H03K19/003

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit (400) includes a precharge device (101) precharging a precharge node (110) during a precharge phase and a logic block (121,123,125,127,129) receiving plural input signals (A,B,C,D,E) to conditionally discharge the precharge node. In this improvement a second precharge device (150) precharges an intermediate node (122) when a particular input signal (E) controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device (114) according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device (155) controlled by a second input signal (D) different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node. If the input signal controlling the second precharge device is unconstrained, then the circuit preferably includes a clock controlled precharge device to precharge the intermediate node during the precharge phase and a discharge control device disposed between said logic block and ground preventing discharge during the precharge phase. Alternatively, the input signal may be clocked and guaranteed low during the precharge phase. In this case, the clocked precharge of the intermediate node and the discharge control device are optional.