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    Method and apparatus for multiplying a plurality of N numbers
    34.
    发明公开
    Method and apparatus for multiplying a plurality of N numbers 失效
    Verfahren und Anordnung zum Multiplizieren einer Mehrzahl von N-Zahlen

    公开(公告)号：EP0686911A1

    公开(公告)日：1995-12-13

    申请号：EP95303670.4

    申请日：1995-05-30

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： Mondul, Donald D. ,  Asghar, Safdar M.

    IPC分类号： G06F7/49 ,  G06F7/52 ,  G06F1/03

    CPC分类号： G06F7/5306 ,  G06F1/03 ,  G06F7/49 ,  G06F7/4915 ,  G06F7/523 ,  G06F7/5235 ,  G06F7/5324 ,  G06F2207/3816

    摘要： A method and apparatus are disclosed for determining the product of N numbers in base Z. The method comprises the steps of: (1) providing a first and succeeding storage arrays. The first storage array includes storage loci containing indicia of products of a first digit and a second digit. A first pointer is positioned by the first digit, a second pointer is positioned by the second digit, and the pointers cooperate to identify a first solution locus containing a first product. Succeeding storage arrays are associated with succeeding N numbers. The first and second pointers identify a subset of storage loci in a succeeding storage array. A third pointer associated with a third digit identifies a second solution locus among the subset. Each array's pointers cooperate to designate a next-succeeding array and a subset of storage loci, and each next-succeeding array has a pointer associated with a next digit to designate a next solution locus until N numbers are involved in the product. Each succeeding array stores indicia of the product of the digit of the number associated with that array and the product identified by the preceding array; (2) determining a partial product for each combination of the digits of each of the N numbers, each partial product having a combinational significance established by the significance of each digit involved; (3) accumulating partial products in hierarchically arranged cells according to a particular relationship; and (4) effecting a shifting accumulation operation among the cells.

    摘要翻译： 公开了一种用于确定基座Z中N个数的乘积的方法和装置。该方法包括以下步骤：（1）提供第一和后续存储阵列。 第一存储阵列包括包含第一数字和第二数字的产品的标记的存储轨迹。 第一指针由第一数字定位，第二指针由第二数位置，并且指针协作以识别包含第一乘积的第一解轨迹。 成功的存储阵列与后续N个数字相关联。 第一个和第二个指针在后续的存储阵列中标识一个存储轨迹的子集。 与第三数字相关联的第三指针识别子集中的第二解轨迹。 每个阵列的指针协作以指定下一个后续阵列和存储轨迹的子集，并且每个下一个后续阵列具有与下一个数字相关联的指针，以指定下一个解决方案轨迹，直到产生N个数字。 每个后续阵列存储与该阵列相关联的数字的数字和由前一个阵列识别的乘积的乘积的标记; （2）确定每个N个数字的数字的每个组合的部分积，每个部分乘积具有由所涉及的每个数字的重要性确定的组合意义; （3）根据特定的关系在分层布置的单元中累积部分乘积; 和（4）在单元之间进行移位累积操作。

    Method and apparatus for multiplying a plurality of numbers
    35.
    发明公开
    Method and apparatus for multiplying a plurality of numbers 失效
    Verfahren und Anordnung zum Multiplizieren einer Mehrzahl von Zahlen。

    公开(公告)号：EP0619542A2

    公开(公告)日：1994-10-12

    申请号：EP94302057.8

    申请日：1994-03-22

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： Asghar, Safdar M. ,  Mondul, Donald D.

    IPC分类号： G06F7/52 ,  G06F7/544

    CPC分类号： G06F7/523 ,  G06F7/5235 ,  G06F7/5324 ,  G06F2207/3816

    摘要： A method and apparatus for determining the product of a plurality of numbers are disclosed. The preferred embodiment of the method comprises the steps of : (1) determining a plurality of respective partial products for each pair-combination of a first number's digits and a second number's digits ; (2) providing a register having a plurality of register cells, each having a hierarchical significance; (3) accumulating selected of the respective partial products to produce accumulated values in specified of the register cells according to the following relationships: P m,n ―[accumulates in]→ r x ; x=(m+n)-1, where "P m,n " represents the respective partial product ; "m" represents the first number's significance (m = 1, 2, ...); "n" represents the second number's significance (n = 1, 2, ...); and "r x " represents a specified register cell having significance "x" ; (4) sequentially effecting a shifting accumulation operation comprising shifting specific digits of the accumulated value stored in a lesser-significant register cell to the next-higher-significant register cell containing an accumulated value, and adding the specific digits to the accumulated value stored in the next-higher-significant register cell as least-significant digits between significance-adjacent register cells from the least-significant register cell to the most-significant register cell ; (5) iteratively applying the contents of the register to repeat steps (1) through (4) with a succeeding next number until all of the plurality of new numbers have been employed by the method and (6) shifting the contents of the register from the register.

    摘要翻译： 公开了一种用于确定多个数字的乘积的方法和装置。 该方法的优选实施例包括以下步骤：（1）确定第一个数字和第二个数字的每个组合的多个相应的部分乘积; （2）提供具有多个寄存器单元的寄存器，每个寄存器单元具有分层意义; （3）根据以下关系累积选定的各个部分乘积以产生指定的寄存器单元中的累加值：Pm，n- [累加] - > rx; x =（m + n）-1，其中“Pm，n”表示各自的部分乘积; “m”表示第一个数字的意义（m = 1,2，...）; “n”表示第二个数字的意义（n = 1,2，...）; 而“rx”表示具有重要性“x”的指定寄存器单元; （4）顺序地进行移位累积操作，包括将存储在较低有效寄存器单元中的累加值的特定数字移位到包含累加值的下一个高有效寄存器单元，并将特定数字加到存储在 下一个较高有效寄存器单元作为从最低有效寄存器单元到最高有效寄存器单元的有效相邻寄存器单元之间的最低有效数字; （5）迭代地应用寄存器的内容重复步骤（1）至（4），并重复下一个号码，直到所有这些新的号码都被该方法使用，并且（6）将寄存器的内容从 登记册。

    Apparatus for controlling power delivery to selected portions of a multiplying device
    37.
    发明公开
    Apparatus for controlling power delivery to selected portions of a multiplying device 失效
    Vorrichtung zur Steuerung der Stromversorgung zu selektierten Teilen eines Multiplikationswerks。

    公开(公告)号：EP0583120A1

    公开(公告)日：1994-02-16

    申请号：EP93306060.0

    申请日：1993-07-30

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Asghar, Safdar M. ,  Mondul, Donald D.

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3816

    摘要： An apparatus for controlling power delivery from a power source to selected portions of a multiplying device for determining the product of a first number having a first plurality of digits and a second number having a second plurality of digits. The multiplying device comprises a plurality of components which include a plurality of multiplier units for determining a plurality of partial products and a register unit for storing information, the register unit including plurality of register cells for accumulatingly storing the partial products according to a predetermined arrangement; the apparatus comprises: a power bus for providing controllable delivery paths for delivering the power from the power source to the multiplying device; and a control unit for controlling the delivery paths to selectively effect operational connection between specified components and the power source. The control unit includes a logic unit for comparing the first number with the second number and determining the greater number of digits between the first number and the second number. The control unit employs the greater number of digits to selectively provide the power to specified components of the plurality of components.

    摘要翻译： 一种用于控制从电源到乘法装置的选定部分的功率传送的装置，用于确定具有第一多个数字的第一号码和具有第二多个数字的第二号码的乘积的乘积。 所述乘法装置包括多个分量，其包括用于确定多个部分乘积的多个乘法器单元和用于存储信息的寄存器单元，所述寄存器单元包括用于根据预定布置累积存储所述部分乘积的多个寄存器单元; 该装置包括：电源总线，用于提供用于将电力从电源传送到乘法装置的可控输送路径; 以及控制单元，用于控制传送路径以选择性地影响指定部件和电源之间的操作连接。 控制单元包括一个逻辑单元，用于将第一个数字与第二个数字进行比较，并确定第一个数字和第二个数字之间的较大数字位数。 控制单元使用较大数量的位数来选择性地向多个组件的指定组件提供功率。

    Serial digital signal processing circuitry
    38.
    发明公开
    Serial digital signal processing circuitry 失效
    串行数字信号处理电路

    公开(公告)号：EP0238300A3

    公开(公告)日：1990-09-12

    申请号：EP87302260.2

    申请日：1987-03-17

    申请人： RCA Thomson Licensing Corporation

    发明人： McClary, Dennis Roy ,  Dieterich, Charles Benjamin

    IPC分类号： G06F5/06 ,  G06F7/48

    CPC分类号： G06F5/08 ,  G06F7/48 ,  G06F7/49994 ,  G06F2207/3816

    摘要： A serial-bit digital processing system uses registers and latches to synchronize samples and justify sign-bits. Nominally each processing block in the system includes a sign extend register (16) preceding an arithmetic element (18) and an output register (20) following the arithmetic element. Input registers of one arithmetic element may merge with output registers of the preceding arithmetic element. The sign extend registers include a serially coupled latch which is selectively controlled to pass serial sample bits or to replicate the sign bit. The respective registers are clocked with one of two clock signals (CLOCKN, CLOCKP) having different numbers of pulses per sample period and the length of the respective registers are selected so that at the terminus of each sample period the bits of each sample in the processing system are appropriately justified.

    An arithmetic logic unit for a graphics processor
    39.
    发明公开
    An arithmetic logic unit for a graphics processor 失效
    Arithmetisch logische Einheitfüreinen Grafikprozessor。

    公开(公告)号：EP0385568A2

    公开(公告)日：1990-09-05

    申请号：EP90300502.3

    申请日：1990-01-18

    申请人： International Business Machines Corporation

    发明人： Bates, Mathew Damien ,  West, Roderick Michael ,  Gay, Adrian Charles ,  Butler, Nichola David ,  Kim, Jong Han

    IPC分类号： G06F7/50

    CPC分类号： G06F7/505 ,  G06F9/30036 ,  G06F2207/3816 ,  G06F2207/3828

    摘要： A digital arithmetic logic unit is described in which the carry chain (6) is subdivided into a series of bit-fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit-fields. Division of the carry chain is achieved via a carry chain selector (7) consisting of a series of multiplexers (9), one being placed between each stage (FA) of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of the bit-field and forms the least significant bit of the next bit-field. This selection of the carry by the multiplexer is under control of a programmable register (8), thus allowing variable division of the carry chain.

    摘要翻译： 描述了数字算术逻辑单元，其中进位链（6）被细分为一系列位域，允许在每个位域中进行独立且同时的数据操作。 通过由一系列多路复用器（9）组成的进位链选择器（7）实现进位链的分割，一个放置在进位链的每个阶段（FA）之间。 每个复用器具有两个数据输入，其中一个形成进位链的下一个进位。 选择的进位可以继续计算或定义位域的结束，并形成下一个位域的最低有效位。 多路复用器的进位选择在可编程寄存器（8）的控制下，从而允许进位链的可变划分。