公开(公告)号：EP0461214A4

公开(公告)日：1993-09-01

申请号：EP90917368

申请日：1990-11-13

申请人： MOTOROLA, INC.

发明人： LINDSLEY, BRETT, LOUIS

IPC分类号： G06F7/552 ,  G06F7/38

CPC分类号： G06F7/5525 ,  G06F2207/5521

摘要： A method and apparatus is disclosed that utilizes ''Lindsley's Law'', a polynomial convergence algorithm, suitable even for high convergence rates, to implement more efficient reciprocal j root, and hence, j root itself, computations of desired inputs. The invention emphasizes multiplication (114, 116, 118, 120), instead of addition, as the iterative operator, thereby reducing error at a rate relative to a power of a selected convergence rate.

公开(公告)号：EP0412565A3

公开(公告)日：1992-08-12

申请号：EP90115412.0

申请日：1990-08-10

申请人： SHARP KABUSHIKI KAISHA

发明人： Yoshida, Kunio

IPC分类号： G06F7/552

CPC分类号： G06F7/5525

摘要： An apparatus for calculating the cube root of a number is disclosed. The apparatus has: a first memory for initially storing a cube root extraction number from which the cube root is to be extracted; a second memory for initially storing a first number which is predetermined based on said cube root extrac­tion number; a third memory for initially storing a second predetermined number; a fourth memory for ini­tially storing a third predetermined number; and a fifth memory means for storing a number. The relation in size between the number stored in the first memory and the number stored in the second memory is judged. When the number stored in the first memory is not smaller than the number stored in the second memory, the number stored in the second memory from the number stored stored in the first memory, a number generated from the number stored in the third memory is aded to the number stored in the second memory means, and a fourth predetermined number is added to the number stroed in the fifth memory. When the number stored in the first memory is smaller than the number stored in the second memory, a number generated from the number stored in the fourth memory is subtracted from the number stored in the second memory, and the number stores in the fifth memory is shifted to the left. Until predetermined conditions are met, the above processes are repeated, and the number stored in said fifth memory is determined as the cube root.

公开(公告)号：EP0461214A1

公开(公告)日：1991-12-18

申请号：EP90917368.0

申请日：1990-11-13

申请人： MOTOROLA, INC.

发明人： LINDSLEY, Brett, Louis

IPC分类号： G06F7

CPC分类号： G06F7/5525 ,  G06F2207/5521

摘要： L'invention a pour objet un procédé et un système utilisant la ''Loi de Lindsley'', algorithme de convergence polynôme, adaptable même aux taux de convergence élevés, pour mettre en application une racine jème inverse plus efficace et, de ce fait, la racine jème elle-même, pour calculer des quantités désirées. L'invention met l'accent sur la multiplication (114, 116, 118, 120) au lieu de l'addition, en tant qu'opérateur itératif, de ce fait réduisant l'erreur à un taux relatif à une puissance d'un taux de convergence sélectionné.

公开(公告)号：EP0416309A2

公开(公告)日：1991-03-13

申请号：EP90115266.0

申请日：1990-08-09

申请人： CYRIX CORPORATION

发明人： Briggs, Willard Stuart ,  Brightman, Thomas B. ,  Matula, David William

IPC分类号： G06F7/552

CPC分类号： G06F7/5525

摘要： A method and apparatus for performing the square root function is described which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. Succeeding exact remainders are calculated as the difference between the previous remainder and the product of the newly calculated root digit value and the sum of the newly calculated root digit value and twice the previous partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders. If the corresponding final remainder is negative, the final full precision partial root is decremented and the remainder recalculated, yielding the full precision unique partial root and non-negative remainder pair which compose the exact square root.

摘要翻译： 一种用于执行平方根函数的方法和装置进行说明，其包括第1近似的操作数的平方根的倒数短。 倒数偏压调整因子被添加到近似和截断以形成偏置正确短倒数的结果。 短倒数然后-乘以操作数的最显著预定比特数和产品被适当地截短，以产生第一根数位值。 乘法发生在具有与具有多个比特实质上一样大的全精度希望的根所需要的比特数的长边的矩形的纵横比的乘法器阵列。 乘法器阵列的短边具有一数目的位的稍大由比单个根数字值所需要的比特数几个保护位，所有这一切都被如此确定的开采是位在短期倒数的数量。 根数位值被平方和确切的正方形从操作数减去以得到准确到剩余。 随后新的根数位值是确定的由适当地移位当前余乘以短倒数，选择性地添加一个数字偏置调整系数和截断产物开采。 根数位值被适当地移位和积累，形成了局部的根。 随后精确余数被计算为前一剩余时间和新计算出的根数字值的乘积和新计算出的根数位值之和的两倍先前部分根之间的差。 重复所述步骤，以产生串行根数位值和局部根用新的对应的精确的余。 如果对应的最终余数为负时，最终全精度局部根被递减，其余重新计算，得到全精度独特局部根和非负剩余一对组成的精确平方根。

公开(公告)号：EP0395240A2

公开(公告)日：1990-10-31

申请号：EP90303654.9

申请日：1990-04-05

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Steiss, Donald E. ,  Hipona, Maria B. ,  Darley, Henry M.

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/48

CPC分类号： G06F7/5324 ,  G06F7/535 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/382 ,  G06F2207/5355

摘要： Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48)(50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

摘要翻译： 使用用于接收操作数N的操作数路由电路（16）和操作数D和种子值S并将操作数和种子值引导到乘法器（38）来执行除法和平方根计算。 单个乘法器（38）被配置为两个阵列，用于计算N和S以及D和S的部分乘积。乘法器（38）的结果通过开关电路（20）或寄存器（48）（50）传输到操作数路由 电路（16）或加法器（44）。 最后的结果是四舍五入的。

公开(公告)号：EP0218971A3

公开(公告)日：1990-04-11

申请号：EP86113280.1

申请日：1986-09-26

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Busch, Hans-Joachim, Dipl.-Ing.

IPC分类号： G06F1/02 ,  G06F7/552

CPC分类号： G06F7/5525 ,  G06F1/0356 ,  G06F7/552 ,  G06F2101/08 ,  G06F2207/5525

摘要： Zur Lösung der Gleichung erfolgt in einem ersten Schritt die Verarbeitung der unabhängigen und abhängigen Veränderlichen x 1 , x,...x n , z zur Bestimmung des Radikanten unter Verwendung digitaler Bausteine eines Rechners durch Ausführen elementarer Rechnungsoperationen und durch Potentieren. In einem weiteren Verfahrensschritt wird ein genäherter Anfangs-Lösungswert für die abhängige Veränderliche z berechnet und in einem Komparator mit dem errechneten Wert des Radikanten verglichen. Durch rekursive Iteration des genäherten Wertes der abhängigen Veränderlichen z in einer auf den Komparator rückgekoppelten Schaltung mit einem Demultiplexer mit einem Zähler, einem Speicher und einem Register sowie einer Ablaufsteuerung erfolgt eine sukzessive Approximation der Gleichung.

摘要翻译： 为了实现直接昂格尔跟随在第一步骤中，自变量和因变量x1，X，... X N，Z，用于确定使用计算机的数字模块通过执行基本算术运算，并通过加强被开方的处理。 在另一个方法步骤中，计算因变量z的近似初始解值并在比较器中与基数的计算值进行比较。 通过在反馈到比较器电路与具有计数器，存储器和寄存器，和一个序列的多路分解器因变量z的近似值的递归迭代控制逐次近似式进行。

公开(公告)号：EP0326415A2

公开(公告)日：1989-08-02

申请号：EP89300821.9

申请日：1989-01-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Darley, Henry M. ,  Gill, Michael C. ,  Earl, Dale C. ,  Ngo, Dinh T. ,  Wang, Paul C. ,  Hipona, Maria B. ,  Dodrill, Jim

IPC分类号： G06F7/49 ,  G06F7/52 ,  G06F7/552

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/5525 ,  G06F2207/5355

摘要： A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output from the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessary to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

摘要翻译： 可操作以计算除法和平方根函数的处理器（10）包括具有乘法器阵列（116），流水线寄存器（50），校正发生器（122）和转换器/舍入器（52）的乘法器（48）。 由乘法器阵列（116）产生的乘积被反馈到乘法器（48）以避免与乘法器电路的其余部分相关联的延迟。 执行从乘法器阵列（116）输出的乘积从常数的减法的校正发生器（122）设置在乘法器阵列（116）和转换器/回转器（52）之间。 因此，可以与其他乘法并行地执行计算下一估计所需的减法，进一步减少执行计算所需的时间。 比较电路（120）可操作以将最终近似与操作数进行比较，以快速确定舍入方向。

公开(公告)号：EP0218971A2

公开(公告)日：1987-04-22

申请号：EP86113280.1

申请日：1986-09-26

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Busch, Hans-Joachim, Dipl.-Ing.

IPC分类号： G06F1/02 ,  G06F7/552

CPC分类号： G06F7/5525 ,  G06F1/0356 ,  G06F7/552 ,  G06F2101/08 ,  G06F2207/5525

摘要： Zur Lösung der Gleichung erfolgt in einem ersten Schritt die Verarbeitung der unabhängigen und abhängigen Veränderlichen x 1 , x,...x n , z zur Bestimmung des Radikanten unter Verwendung digitaler Bausteine eines Rechners durch Ausführen elementarer Rechnungsoperationen und durch Potentieren. In einem weiteren Verfahrensschritt wird ein genäherter Anfangs-Lösungswert für die abhängige Veränderliche z berechnet und in einem Komparator mit dem errechneten Wert des Radikanten verglichen. Durch rekursive Iteration des genäherten Wertes der abhängigen Veränderlichen z in einer auf den Komparator rückgekoppelten Schaltung mit einem Demultiplexer mit einem Zähler, einem Speicher und einem Register sowie einer Ablaufsteuerung erfolgt eine sukzessive Approximation der Gleichung.

摘要翻译： 为了求解方程，通过使用计算机的数字分量进行基本数学运算和乘幂运算，第一步骤处理独立和相关变量x1，x2 ... xn，z用于确定自由基。 在另一个方法步骤中，对因变量z计算近似的初始解值，并与比较器中的radicand的计算值进行比较。 通过使用包括计数器，存储器和寄存器以及序列控制的解复用器的具有反馈给比较器的电路中的因变量z的近似值的递归迭代来获得等式的逐次逼近。

公开(公告)号：EP3159788B1

公开(公告)日：2018-08-29

申请号：EP16194577.9

申请日：2016-10-19

申请人： Imagination Technologies Limited

发明人： VAN BENTHEM, Casper ,  ELLIOTT, Sam

IPC分类号： G06F7/499 ,  G06F7/552

CPC分类号： G06F7/483 ,  G06F7/49947 ,  G06F7/49963 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/5521

摘要： Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term. To be accompanied, when published, by FIG. 3 of the accompanying drawings.

公开(公告)号：EP3286635A1

公开(公告)日：2018-02-28

申请号：EP16714722

申请日：2016-03-28

申请人： QUALCOMM INC

发明人： DIBRINO MICHAEL THOMAS ,  DOCKSER KENNETH ALAN ,  LALL PATHIK SUNIL

IPC分类号： G06F7/537 ,  G06F7/552

CPC分类号： G06F7/52 ,  G06F7/537 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

摘要： Systems and methods relate to a division/root computation unit. A lookup table according to a Sweeney, Robertson, and Tocher (SRT) algorithm for a division/root computation is stored in a memory. Information related to a selected column corresponding to a divisor/root estimate is stored in a high-speed memory. Division/root computation is performed iteratively using the cached information to improve access times and reduce latency of accessing the entire lookup table on each iteration. In each iteration, a quotient/root is determined from the cached information based on a current partial remainder, and a next partial remainder is generated based on the quotient/root, the divisor/root estimate, and the current partial remainder.