公开(公告)号：EP0929077A2

公开(公告)日：1999-07-14

申请号：EP99104096.5

申请日：1994-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ohsawa, Takashi ,  Fujii, Shuso

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/08 ,  G11C29/24 ,  G11C29/34 ,  G11C29/40 ,  G11C29/44

Abstract: A semiconductor memory comprising a memory cell block 111 comprising a plurality of memory cells, having n pairs of parallel bit structure; two pairs of word lines WL connected to said memory cells of said memory cell block; n pairs of bit lines BL, /BL connected to said memory cells of said memory cell block; n pairs of DQ data lines DQ05, /DQ05 - DQ35, /DQ35 connected to said n pairs of bit lines and divided into two groups each comprising n/2 pairs of the DQ data lines, a group of n/2 pairs of the DQ lines being arranged at a side of said memory cell block and another group of n/2 pairs of the DQ lines being arranged at an opposite side of said memory cell block.

Abstract translation: 一种半导体存储器，包括：存储单元块111，包括多个存储单元，具有n对并行位结构; 连接到所述存储单元块的所述存储单元的两对字线WL; 连接到所述存储单元块的所述存储单元的n对位线BL，/ BL; n对连接到所述n对位线并分成两组的每对DQ数据线DQ05，/ DQ05-DQ35，/ DQ35，每组包括n / 2对DQ数据线，一组n / 2对DQ 在所述存储器单元块的一侧安排线，并且在所述存储器单元块的相对侧安排另一组n / 2对DQ线。

公开(公告)号：EP0472266B1

公开(公告)日：1997-07-30

申请号：EP91304951.6

申请日：1991-05-31

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/34 ,  G11C29/38

公开(公告)号：EP0558231A3

公开(公告)日：1995-07-12

申请号：EP93301137.1

申请日：1993-02-17

Applicant: NEC CORPORATION

Inventor： Ohkawa, Shin-ichi, c/o NEC Corporation

IPC: G01R31/318 ,  G11C29/00

CPC classification number: G11C29/38 ,  G01R31/318505 ,  G11C29/28

Abstract: A device for testing a plurality of functional blocks such as RAM macros (13-1 through 13-m) in a semiconductor integrated circuit inputs plural kinds of testing signals necessary for testing the functional blocks from the exterior, and stores the testing signals to one register (11) or one latch to supply the testing signals in common to each of the functional blocks via a testing signal bus (AT,DIT,WET,BST). Thus, the plural functional blocks concurrently operate, and output their response signals. A multiplexor (15) selects one of those response signals and outputs it as the test output signal of the corresponding functional block.

Abstract translation: 用于测试半导体集成电路中的诸如RAM宏（13-1至13-m）的多个功能块的设备输入从外部测试功能块所需的多种测试信号，并将测试信号存储到一个 寄存器（11）或一个锁存器，以经由测试信号总线（AT，DIT，WET，BST）将测试信号共同提供给每个功能块。 这样，多个功能块同时工作，并输出它们的响应信号。 多路复用器（15）选择那些响应信号中的一个并将其输出作为相应功能块的测试输出信号。

公开(公告)号：EP0617429A2

公开(公告)日：1994-09-28

申请号：EP94100993.8

申请日：1994-01-24

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori, c/o NEC Corporation

IPC: G11C29/00

CPC classification number: G11C29/38 ,  G11C29/26 ,  G11C29/28

Abstract: A semiconductor memory device is disclosed which has a data output circuit including a first node, a second node, first and second transistors connected in series between the first node and a potential line, third and fourth transistors connected in series between the first node and the potential line, fifth and sixth transistors connected in series between the second node and the potential line, seventh and eighth transistors connected in series between the second node and the potential line, one of the first and third transistors being driven in response to a data signal read from a selected memory cell and one of the fifth and seventh transistors being driven in response to an inverted data signal of the data signal in a normal mode while turning one of the second and fourth transistor and one of the sixth and eighth transistors ON, both of the first and third transistors being driven in response to the data signal and both of the fifth and seventh transistors being driven in response to the inverted data signal while all the second, fourth, sixth and eighth transistors ON. The output circuit further includes an output logic circuit driving an output terminal to one of first and second logic levels when the first and second nods have logic levels different from each other and to a high impedance when the first and second nodes have logic levels equal to each other.

Abstract translation: 公开了一种半导体存储器件，其具有包括串联连接在第一节点和电位线之间的第一节点，第二节点，第一和第二晶体管的数据输出电路，串联连接在第一节点和第一节点之间的第三和第四晶体管 串联连接在第二节点和电位线之间的电位线，第五和第六晶体管，第七和第八晶体管串联连接在第二节点和电位线之间，第一和第三晶体管之一响应于数据信号被驱动 从所选择的存储单元读取并且响应于在正常模式下的数据信号的反相数据信号驱动第五和第七晶体管中的一个，同时将第二和第四晶体管中的一个和第六和第八晶体管中的一个导通， 响应于数据信号驱动第一和第三晶体管两者，并且第五和第七晶体管都以响应方式被驱动 同时所有第二，第四，第六和第八晶体管ON。 输出电路还包括输出逻辑电路，当第一和第二点具有彼此不同的逻辑电平时，将输出端驱动到第一和第二逻辑电平中的一个，并且当第一和第二节点的逻辑电平等于 彼此。

公开(公告)号：EP0472266A3

公开(公告)日：1993-03-10

申请号：EP91304951.6

申请日：1991-05-31

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/34 ,  G11C29/38

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals. The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.

公开(公告)号：EP0448364A3

公开(公告)日：1992-04-29

申请号：EP91302384.2

申请日：1991-03-19

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Wada, Tomohisa, Mitsubishi Denki K.K. ,  Murakami, Shuji, Mitsubishi Denki K.K.

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/28

Abstract: A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.

公开(公告)号：EP0448364A2

公开(公告)日：1991-09-25

申请号：EP91302384.2

申请日：1991-03-19

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Wada, Tomohisa, Mitsubishi Denki K.K. ,  Murakami, Shuji, Mitsubishi Denki K.K.

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/28

Abstract: A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.

Abstract translation: 包括多个具有存储单元阵列的块的半导体存储装置包括在多个块中的每一个中提供的异或电路，用于确定写入块中的存储单元中的数据是否正常读取。 多个存储单元阵列块的异或电路连接到OR电路。 利用来自OR电路的输出信号，确定多个存储单元阵列块是否正常。 由于来自多个存储单元阵列块的测试数据由OR电路同时检查，所以可以减少半导体存储器件的测试时间。

公开(公告)号：EP0232641A3

公开(公告)日：1989-06-14

申请号：EP86402738.8

申请日：1986-12-10

Applicant: ITT INDUSTRIES INC.

Inventor： Morton, Steven Gregory

IPC: G06F15/06

CPC classification number: G06F11/2051 ,  G01R31/318505 ,  G06F15/8007 ,  G11C29/28

Abstract: In a cellular array processor at least two of the plurality of processors in a row cooperate together as an address generator so that large amounts of memory external to the array chip may be addressed and in addition so that an address may be generated onboard for use by the DRAM memory associated with each processor. Based on this structure, a memory with an internal organization that is 256-bits wide may be connected to 16 16-bit processors which would require 256 bits of data. In so doing, a vast number of pins are saved, that is 256 bits of data out of the memory and 256 bits of data into the processing cells by combining the processing cells and memory on the same chip. It is significant that exactly one design of a processing cell may provide both a data processing element and an address processing element. In this way, these cells are interchangeable to maximize the yield and reliability of the device. A single address from the address generator addresses the entire onboard DRAM so as to use the number of address generators required and to reduce the amount of address decode logic required as well as minimizing power dissipation in the DRAM portion of the chip.

Abstract translation: 在蜂窝阵列处理器中，一行中的多个处理器中的至少两个处理器一起协作作为地址发生器，使得可以寻址阵列芯片外部的大量存储器，并且另外地址使得地址。 可以在板上生成以供与每个处理器相关联的DRAM存储器使用。 基于这种结构，具有256位宽的内部组织的存储器可以连接到需要256位数据的16位16位处理器。 这样做，通过将处理单元和存储器组合在同一芯片上，大量的引脚被保存在存储器中的256位数据和256位数据到处理单元中。 重要的是处理单元的恰好一个设计可以提供数据处理元件和地址处理元件。 以这种方式，这些电池可以互换，以最大限度地提高装置的产量和可靠性。 来自地址发生器的单个地址解决整个板载DRAM，以便使用所需的地址发生器的数量，并且减少所需的地址解码逻辑的数量以及最小化芯片的DRAM部分的功耗。

公开(公告)号：EP0066147B1

公开(公告)日：1988-12-14

申请号：EP82104206.6

申请日：1982-05-13

Applicant: NEC CORPORATION

Inventor： Chiwaki, Yoshinori

IPC: G06F11/20

CPC classification number: G11C29/74 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/141 ,  G06F13/1684 ,  G11C29/28

公开(公告)号：EP0259859A2

公开(公告)日：1988-03-16

申请号：EP87113189.2

申请日：1987-09-09

Applicant: NEC CORPORATION

Inventor： Jippo, Akira c/o NEC Corporation

IPC: G11C29/00 ,  G06F11/20

CPC classification number: G11C29/76 ,  G06F11/22 ,  G11C29/28 ,  G11C29/38

Abstract: In an information processing system for use in detecting an error in a main memory (11) comprising a plurality of memory units (111 to 118) and a common control section (19), an error detection signal and an error address are sent from a request source processor (15) to a diagnostic address generator (31) when an error is detected on an access operation of the request source processor. On diagnostic access operations, the diagnostic address generator successively produces a plurality of diagnostic addresses including the error address to receive diagnostic replies, each of which comprises a reply code. When an error of the main memory is indicated by the reply code, an error detection controller (32) discriminates the diagnostic address on occurrence of the error in the diagnostic operations to disconnect the memory unit or units from the main memory by the use of a memory restructuring circuit (36). All of the memory units are disconnected when a malfunction of the common control section is discriminated by the error detection controller.

Abstract translation: 在用于在包括存储器单元（111〜118）多个和一个共用控制部（19），错误检测信号和错误地址的主存储器（11）中的错误的检测中使用的信息处理系统，是从发送 请求源处理器（15），以当在请求源处理器的访问手术中检测上的误差的诊断地址生成器（31）。 在诊断访问操作，诊断地址发生器先后可生产包括错误地址接收诊断答复，每一个包括回复代码诊断地址的多元性。 当在主存储器的错误是由应答码所指出的，错误检测控制器（32）判断在所述诊断操作的错误的发生的诊断地址通过使用一个断开从主存储器中的存储器单元 存储器重组电路（36）。 所有存储器单元被断开连接当公共控制部的故障是由误差检测控制部区分。