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    Clock signal networks for structured asic devices
    31.
    发明公开
    Clock signal networks for structured asic devices 审中-公开
    高分辨率ASIC-Vorrichtungen

    公开(公告)号：EP1729198A2

    公开(公告)日：2006-12-06

    申请号：EP06009561.9

    申请日：2006-05-09

    申请人： Altera Corporation

    发明人： Lim, Chooi Pei ,  Too, Joo Ming ,  Kok, Yew Fatt (Edwin) ,  Chua, Kar Keng

    IPC分类号： G06F1/10

    CPC分类号： H03K19/1774 ,  G06F1/10

    摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

    摘要翻译： 用于结构化ASIC器件的时钟分配电路包括确定性部分和可配置部分。 确定部分采用预定布置的导体段和缓冲器，用于将时钟信号分配到设备上的多个预定位置。 从每个预定位置，时钟分配电路的相关联的可配置部分将时钟信号分配到在从该预定位置服务的结构化ASIC的预定区域中需要该时钟信号的任何时钟利用电路。

    ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY
    32.
    发明公开
    ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY 有权
    FOR THE方案业务架构剥开门阵列

    公开(公告)号：EP1346478A1

    公开(公告)日：2003-09-24

    申请号：EP01988397.4

    申请日：2001-12-20

    申请人： Quicklogic Corporation

    发明人： FU, Robert ,  EATON, David, D. ,  YEE, Kevin, K. ,  CHAN, Andrew, K.

    IPC分类号： H03K7/08

    CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778 ,  H03L7/183

    摘要： A field programmable gate array (100) includes a programmable interconnect structure (104) and plurality of logic cells (102). The logic cells each include a number of combinatorial logic circuits (110a, 110b), which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element (162, 164), such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells (102) include both combinatorial and registered connections with the programmable interconnect structure (104). Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

    Programmable logic array integrated circuit
    36.
    发明公开
    Programmable logic array integrated circuit 失效
    可编程逻辑阵列集成电路

    公开(公告)号：EP0569137A3

    公开(公告)日：1994-06-29

    申请号：EP93302745.0

    申请日：1993-04-07

    申请人： ALTERA CORPORATION

    发明人： Cliff, Richard G. ,  Lytle, Craig Schilling ,  Ahanin, Bahram ,  Heile, Francis B. ,  Pedersen, Bruce B. ,  Veenstra, Kerry

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    Flexible synchronous/asynchronous cell structure for a programmable logic device
    37.
    发明公开
    Flexible synchronous/asynchronous cell structure for a programmable logic device 失效
    用于可编程逻辑器件的灵活同步/异步电池结构

    公开(公告)号：EP0583872A3

    公开(公告)日：1994-05-11

    申请号：EP93305040.3

    申请日：1993-06-28

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Agrawal, OM P. ,  Llgenstein, Kerry A.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/17716

    摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells (2000A,2000B). The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank (2040A1) and a sub-bank of a programmable input switch matrix bank (2020A1). Each programmable logic block cell includes a multiplicity of product terms (PT0-PT9). At least one product term (PT1, PT2, PT3, PT6, PT7, PT8) in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

    Programmable logic devices
    38.
    发明公开
    Programmable logic devices 失效
    可编程逻辑器件

    公开(公告)号：EP0537885A1

    公开(公告)日：1993-04-21

    申请号：EP92307282.1

    申请日：1992-08-10

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Agrawal, Om P.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

    摘要： An asynchronous high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable output logic macrocells, programmable input/output macrocells, programmable input logic macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the output logic macrocells from the product term array. The logic allocator decouples the product term array from the output logic macrocells, and the I/O macrocells decouple the output logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no logic product terms are permanently allocated to a specific logic macrocell. Each output logic macrocell is provided three dedicated control product terms from the programmable product term array and each I/O macrocell is provided one control product term from the programmable product term array in one embodiment. These four dedicated product terms are used to implement asynchronous applications. Each asynchronous programmable logic device of this invention is derived from the core of a programmable logic device in a family of synchronous programmable logic devices.

    摘要翻译： 异步高密度分段可编程阵列逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程输出逻辑宏单元，可编程输入/输出宏单元，可编程输入逻辑宏单元，逻辑分配器和可编程产品术语阵列。 此外，交换矩阵提供具有固定路径无关延迟的集中式全局路由。 可编程开关互连矩阵将输出逻辑宏单元与产品术语阵列分离。 逻辑分配器将产品术语阵列与输出逻辑宏单元分离，并且I / O宏单元将输出逻辑宏单元与封装I / O引脚解耦。 因此，本发明的体系结构可以容易地扩展到更高密度的器件而不损害速度。 逻辑分配器将产品术语数组中的乘积项引导至选定的逻辑宏单元，以便不将逻辑乘积项永久分配给特定的逻辑宏单元。 在一个实施例中，每个输出逻辑宏单元被提供来自可编程产品术语阵列的三个专用控制产品术语，并且每个I / O宏单元被提供来自可编程产品术语阵列的一个控制产品术语。 这四个专用产品术语用于实现异步应用程序。 本发明的每个异步可编程逻辑器件都从同步可编程逻辑器件系列中的可编程逻辑器件的核心派生而来。

    Integrated circuit
    39.
    发明公开
    Integrated circuit 失效
    Integrierter Schaltkreis。

    公开(公告)号：EP0445909A1

    公开(公告)日：1991-09-11

    申请号：EP91300434.7

    申请日：1991-01-18

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Agrawal, Om P. ,  Landers, George H. ,  Schmitz, Nicholas A. ,  Moench, Jerry D. ,  Llgenstein, Kerry A.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

    摘要： A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix (401) to couple an array of symmetric programmable logic blocks (402A-1,402A-2).Each programmable logic block includes programmable logic macrocells (4122), programmable input/output macrocells (4132), a logic allocator (4112) and a programmable product term array (4102). Further, the switch matrix (401A) provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix (401A) decouples the logic macrocells (4122) from the product term array (4102). The logic allocator (4112) decouples the product term array (4102) from the logic macrocells (4122) and the I/O macrocells (4132) decouple the logic macrocells (4122) from the package I/O pins (403A-1,403A-2). Thus, the architecture if this invention is easily scalable to higher density devices without compromising speed. The logic allocator (4112) steers product terms from the product term array (4102) to selected logic macrocells (4122) so that no product terms are permanently allocated to a specific logic macrocell.

    摘要翻译： 高密度分段可编程阵列逻辑器件利用可编程开关互连矩阵（401）耦合对称可编程逻辑块阵列（402A-1,402A-2）。每个可编程逻辑块包括可编程逻辑宏单元（4122），可编程输入/ 输出宏单元（4132），逻辑分配器（4112）和可编程乘积项阵列（4102）。 此外，开关矩阵（401A）提供具有固定路径独立延迟的集中式全局路由。 可编程开关互连矩阵（401A）将逻辑宏单元（4122）与产品项阵列（4102）分离。 逻辑分配器（4112）将产品项阵列（4102）与逻辑宏单元（4122）分离，并且I / O宏单元（4132）将逻辑宏单元（4122）与封装I / O引脚（403A-1,403A- 2）。 因此，如果本发明可以容易地扩展到更高密度的设备而不牺牲速度，则该架构。 逻辑分配器（4112）将产品术语从产品项阵列（4102）引导到选择的逻辑宏单元（4122），使得不将产品项永久分配给特定逻辑宏单元。

    APPARATUS FOR RECOGNIZING A PULSE SIGNAL
    40.
    发明公开
    APPARATUS FOR RECOGNIZING A PULSE SIGNAL 审中-公开
    用于识别脉冲信号的装置

    公开(公告)号：EP3309634A1

    公开(公告)日：2018-04-18

    申请号：EP17161326.8

    申请日：2017-03-16

    申请人： LSIS Co., Ltd.

    发明人： PARK, Kang-Hee

    IPC分类号： G05B19/05

    CPC分类号： H03K19/1774 ,  G05B19/054 ,  G05B2219/1164 ,  G05B2219/1176 ,  H03K19/17744 ,  H03K19/1776

    摘要： The present disclosure relates to an apparatus for recognizing a pulse signal, and more particularly, to an apparatus for recognizing a pulse signal, which maintains the pulse signal being input for a scan time until an end time point of the scan time, and stores the pulse signal in a pulse signal storage area as pulse input data. The apparatus for recognizing a pulse signal according to one embodiment of the present disclosure includes a signal maintaining unit (120) configured to maintain and output the pulse signal, which is input for the scan time, as a pulse maintaining signal; a signal transmission unit (130) configured to receive the pulse maintaining signal from the signal maintaining unit and transmit the input pulse maintaining signal based on a transmission control signal; and a control unit (140) configured to output the transmission control signal to the signal transmission unit (130) to receive the pulse maintaining signal, and store the received pulse maintaining signal in a pulse signal storage area as pulse input data.

    摘要翻译： 用于识别脉冲信号的装置技术领域本发明涉及一种用于识别脉冲信号的装置，并且更具体地涉及一种用于识别脉冲信号的装置，其保持脉冲信号被输入扫描时间直到扫描时间的结束时间点， 脉冲信号存储区中的脉冲信号作为脉冲输入数据。 根据本公开的一个实施例的用于识别脉冲信号的装置包括：信号保持单元（120），被配置为保持并输出在扫描时间内输入的脉冲信号作为脉冲维持信号; 信号传输单元（130），被配置为从所述信号保持单元接收所述脉冲维持信号，并基于传输控制信号传输所述输入脉冲维持信号; 以及控制单元（140），被配置为向信号传输单元（130）输出传输控制信号以接收脉冲维持信号，并且将接收到的脉冲维持信号作为脉冲输入数据存储在脉冲信号存储区域中。