公开(公告)号：EP0445913A3

公开(公告)日：1992-07-08

申请号：EP91300766.2

申请日：1991-01-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Schmitz, Nicholas A.

IPC分类号： G06F15/60

CPC分类号： G06F17/5054

摘要： Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation means for fitting a logic design to a multiplicity of programmable logic blocks with limited interconnectivity between the modules is provided. The resource allocation means requires minimal programmable logic device resources to achieve the allocation of resources within the programmable logic device to the user logic design. The resource allocation means employs block partitioning means and resource assignment means to map user logic to a programmable logic device (PLD) having multiple programmable AND fixed OR arrays interconnected by a programmable switch matrix, i.e., allocate the PLD resources to the user logic.

公开(公告)号：EP0445909A1

公开(公告)日：1991-09-11

申请号：EP91300434.7

申请日：1991-01-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om P. ,  Landers, George H. ,  Schmitz, Nicholas A. ,  Moench, Jerry D. ,  Llgenstein, Kerry A.

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix (401) to couple an array of symmetric programmable logic blocks (402A-1,402A-2).Each programmable logic block includes programmable logic macrocells (4122), programmable input/output macrocells (4132), a logic allocator (4112) and a programmable product term array (4102). Further, the switch matrix (401A) provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix (401A) decouples the logic macrocells (4122) from the product term array (4102). The logic allocator (4112) decouples the product term array (4102) from the logic macrocells (4122) and the I/O macrocells (4132) decouple the logic macrocells (4122) from the package I/O pins (403A-1,403A-2). Thus, the architecture if this invention is easily scalable to higher density devices without compromising speed. The logic allocator (4112) steers product terms from the product term array (4102) to selected logic macrocells (4122) so that no product terms are permanently allocated to a specific logic macrocell.

摘要翻译： 高密度分段可编程阵列逻辑器件利用可编程开关互连矩阵（401）耦合对称可编程逻辑块阵列（402A-1,402A-2）。每个可编程逻辑块包括可编程逻辑宏单元（4122），可编程输入/ 输出宏单元（4132），逻辑分配器（4112）和可编程乘积项阵列（4102）。 此外，开关矩阵（401A）提供具有固定路径独立延迟的集中式全局路由。 可编程开关互连矩阵（401A）将逻辑宏单元（4122）与产品项阵列（4102）分离。 逻辑分配器（4112）将产品项阵列（4102）与逻辑宏单元（4122）分离，并且I / O宏单元（4132）将逻辑宏单元（4122）与封装I / O引脚（403A-1,403A- 2）。 因此，如果本发明可以容易地扩展到更高密度的设备而不牺牲速度，则该架构。 逻辑分配器（4112）将产品术语从产品项阵列（4102）引导到选择的逻辑宏单元（4122），使得不将产品项永久分配给特定逻辑宏单元。

公开(公告)号：EP0513983A1

公开(公告)日：1992-11-19

申请号：EP92302773.4

申请日：1992-03-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Ilgenstein, Kerry A. ,  Landers, George ,  Moench, Jerry ,  Schmitz, Nicholas A.

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品术语阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语阵列引导到选定的逻辑宏单元，使得没有产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可路由因素。 第二系列PLD具有比第一系列PLD更大的引脚与逻辑比。

公开(公告)号：EP0445909B1

公开(公告)日：1996-07-31

申请号：EP91300434.7

申请日：1991-01-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om P. ,  Landers, George H. ,  Schmitz, Nicholas A. ,  Moench, Jerry D. ,  Llgenstein, Kerry A.

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

公开(公告)号：EP0445913A2

公开(公告)日：1991-09-11

申请号：EP91300766.2

申请日：1991-01-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Schmitz, Nicholas A.

IPC分类号： G06F15/60

CPC分类号： G06F17/5054

摘要： Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation means for fitting a logic design to a multiplicity of programmable logic blocks with limited interconnectivity between the modules is provided. The resource allocation means requires minimal programmable logic device resources to achieve the allocation of resources within the programmable logic device to the user logic design.
The resource allocation means employs block partitioning means and resource assignment means to map user logic to a programmable logic device (PLD) having multiple programmable AND fixed OR arrays interconnected by a programmable switch matrix, i.e., allocate the PLD resources to the user logic.

摘要翻译： 可编程逻辑器件设计软件提供了一种用于在具有由在用户逻辑设计的可编程开关矩阵的逻辑方程互连的可编程逻辑块的多个可编程逻辑设备分配特定资源。 具体地，资源分配装置，用于与设置在所述模块之间的有限的互连性拟合逻辑设计到可编程逻辑块的多个。 该资源分配装置需要最少的可编程逻辑器件资源到所述可编程逻辑装置到用户逻辑设计中实现了资源的分配。 该资源分配装置采用块分割装置和资源分配装置以用户逻辑映射到具有多个可编程与固定或通过可编程开关矩阵相互连接的阵列的可编程逻辑器件（PLD），即，分配资源PLD给用户的逻辑。