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    IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER
    31.
    发明公开
    IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER 审中-公开

    公开(公告)号：EP3761508A2

    公开(公告)日：2021-01-06

    申请号：EP20183511.3

    申请日：2020-07-01

    Applicant: STMicroelectronics International N.V.

    Inventor： GOYAL, Avneep Kumar

    IPC: H03K5/135 ,  H03K19/003 ,  H04L7/00

    Abstract: A synchronizer circuit (300A) includes a first synchronizer (306A) having a first input (A) for receiving a signal associated with a first clock signal (CLK_A), a second input for receiving a second clock signal (CLK_B), and an output (Z1) for providing a synchronizer circuit output signal (SYNCH_O/P); a second synchronizer (308A) having a first input for receiving the signal associated with the first clock signal (CLK_A), a second input for receiving the second clock signal (CLK_B), and an output (Z2); a detection stage (310A) having a first input coupled to the output of the first synchronizer (306A) and to the output of the second synchronizer (308A), a second input for receiving the second clock signal (CLK_B), and an output (Z4); and a fault output stage (312A) having a first input (Z4) coupled to the detection stage (310A), a second input for receiving the second clock signal (CLK_B),, and an output for providing a fault output signal (FAULT_O/P).

    ASSOCIATION DE TRANSISTORS EN SÉRIE
    33.
    发明公开
    ASSOCIATION DE TRANSISTORS EN SÉRIE 审中-公开

    公开(公告)号：EP3731414A1

    公开(公告)日：2020-10-28

    申请号：EP20171008.4

    申请日：2020-04-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： FROIDEVAUX, Nicolas ,  LOPEZ, Laurent

    IPC: H03K19/003 ,  H03K19/0185 ,  H03K17/30

    Abstract: La présente description concerne un dispositif comportant, en série (71) :
    un premier transistor (73) MOS de type P ;
    un deuxième transistor (75) MOS de type N, connecté au premier transistor (71) ; et
    un troisième transistor (77), connecté au deuxième transistor (75), ledit troisième transistor (77) étant commandé par un signal numérique,
    dans lequel la grille (733) du premier transistor (73) et la grille (753) du deuxième transistor (75) sont interconnectées et destinées à recevoir un potentiel (VDD) d'alimentation d'une puce.

    DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION
    35.
    发明公开
    DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION 审中-公开

    公开(公告)号：EP3588779A1

    公开(公告)日：2020-01-01

    申请号：EP18305800.7

    申请日：2018-06-22

    Applicant: MENTA

    Inventor： PETITHOMME, Stéphane

    IPC: H03K19/003 ,  G06F9/38

    Abstract: A flexible Digital Signal Processor module comprises a Filter unit comprising a multiplier and an adder, where the multiplier receives input from a memory and a Shift Register Lookup table. The Digital Signal Processor module may implement digital filters such as FIR or IIR filters by providing suitable filter coefficients from the memory and data values from the Shift Register Lookup table. An optional state machine may ensure synchronisation of addressing of the memory Shift Register Lookup table, and between multiple instances of the Digital Signal Processor module where these are required for a particular filter implementation. The proposed architecture offers additional modes of operation in which operations other than filter implementations are supported.

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