利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

63 条记录 (耗时 0.014 秒)

    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR, AND THREE-DIMENSIONAL MEMORY
    34.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR, AND THREE-DIMENSIONAL MEMORY 审中-公开

    公开(公告)号：EP4266369A1

    公开(公告)日：2023-10-25

    申请号：EP22778678.7

    申请日：2022-03-22

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： HU, Siping

    IPC分类号： H01L27/11578

    摘要： The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device comprises a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell comprises a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell.

    VERTICAL MEMORY DEVICE
    36.
    发明公开
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：EP4105992A2

    公开(公告)日：2022-12-21

    申请号：EP22178985.2

    申请日：2022-06-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： KWON, Yongseok ,  RHO, Youngsik ,  PARK, Sangwon ,  SEO, Sungwhan ,  LEE, Dongkyu ,  JEONG, Jaeyong

    IPC分类号： H01L27/11578 ,  H01L27/11526 ,  H01L25/065 ,  H01L23/00 ,  H01L49/02

    摘要： A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

    MEMORY ARRAY STAIRCASE STRUCTURE
    40.
    发明公开
    MEMORY ARRAY STAIRCASE STRUCTURE 审中-公开

    公开(公告)号：EP3945582A1

    公开(公告)日：2022-02-02

    申请号：EP21188619.7

    申请日：2021-07-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： LIN, Meng-Han ,  CHIA, Han-Jong ,  WANG, Sheng-Chen ,  YANG, Feng-Cheng ,  LIN, Yu-Ming ,  LIN, Chung-Te

    IPC分类号： H01L27/11551 ,  H01L27/11578

    摘要： Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.