公开(公告)号：EP0300698A3

公开(公告)日：1990-08-01

申请号：EP88306498.2

申请日：1988-07-15

申请人： FUJITSU LIMITED

发明人： Kokado, Masayuki

IPC分类号： H03K19/086 ,  H03K19/013

CPC分类号： H03K19/0136 ,  H03K19/001 ,  H03K19/086

摘要： An emitter coupled logic circuit includes variable impedance circuit (20) which is connected to at least one of two output terminals of the ECL circuit for variably providing an impedance connected to the one output terminal. An impedance to be provided when both the levels of the two outputs are at a high-level is set to be smaller than an impedance to be provided when at least one of the two outputs is at a low-level.

公开(公告)号：EP0367612A3

公开(公告)日：1990-07-25

申请号：EP89311372.0

申请日：1989-11-02

申请人： MOTOROLA, INC.

发明人： Schucker, Douglas W. ,  Weaver, David B. ,  Hickman, Pat ,  Seelback, Walter C.

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/0136

摘要： An ECL transient driver discharges a capacitive load (19) at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load (19). A pull-up transistor (28) is coupled to an output terminal (29) for selectively supplying a voltage thereto in response to a first signal from a logic circuit (11). A pull-down transistor (31) is coupled to the output terminal (29) for selectively sinking a current therefrom in response to a second signal. A comparator circuit (17) is coupled to the pull-down transistor (31), the logic circuit (11), and the output terminal (29), for selectively providing the second signal in response to the first signal and an output voltage on the output terminal (29).

公开(公告)号：EP0250007A3

公开(公告)日：1989-12-27

申请号：EP87200416.3

申请日：1987-03-06

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Tavana, Danash M. ,  Wong, Sing Y.

IPC分类号： H03K19/088 ,  H03K19/013

CPC分类号： H03K19/0136 ,  H03K19/088

摘要： A TTL buffer circuit (30) which is switched by an increasing or decreasing voltage input signal (Ii) at the same threshold, and which switches at increased speed. A bleed transistor (Q6) allows the phase splitter transistor base to begin charging before the bleed transistor (Q6) turns on. While the phase splitter transistor (Q3) is on, the bleed transistor current is limited to avoid interfering with operation of the phase splitter transistor (Q3). When the phase splitter control lead current is cut off, the phase splitter base capacitance is discharged rapidly through the bleed transistor (Q6), at the end of which the phase splitter and bleed transistors (Q3, Q6) stop conducting.

公开(公告)号：EP0336396A3

公开(公告)日：1989-12-13

申请号：EP89105975.0

申请日：1989-04-05

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Fujita, Katsuji c/o Patent Division K.K. TOSHIBA

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/013 ,  H03K19/086

摘要： The present invention discloses a non-saturation type logic circuit including a logic circuit section (10) comprising a plurality of input transistors (13, 14) of a first polarity having their emitters commonly connected to a first current source (16) and their bases connected to receive their corresponding input signals and a first transistor (15) of the first polarity having its emitter connected to the first current source (16) and its base connected to be supplied with a reference voltage, an output circuit (30) second and third tran­sistors (31, 32) of the first polarity having their bases commonly connected to the collector of the first transistor (15) in the logic circuit section and sup­plied with an output signal from the logic circuit sec­tion (10), a second current source (34) connected to the emitter of the second transistor (31), and a fourth transistor (35) of a second polarity having its emitter connected to the third transistor (32) and its base con­nected to the emitter of the second transistor (31) in which, when the second and third transistors (31, 32) are turned OFF, the fourth transistor (35) is turned ON due to electric current supplied from the second current source (34), and a load capacitor (20) which is charged by electric current from the third transistors (32) and discharged to gound through the fourth transistor (35).

公开(公告)号：EP0155313B1

公开(公告)日：1989-11-23

申请号：EP84903510.0

申请日：1984-09-06

申请人： ADVANCED MICRO DEVICES, INC.

发明人： VARADARAJAN, Hemmige, D.

IPC分类号： H03K19/013 ,  H03K19/082

CPC分类号： H03K19/013 ,  H03K19/082

摘要： In a logic gate (14) having input transistors (QA, QB) each with a collector electrode at a first node (1) (which serves as a signal output node), an emitter electrode at a second node (2) to which all emitters are coupled and a base electrode for receiving binary logic signal input, and further having a load resistor (RL) between the first node (1) and a supply voltage coupling (VCC), the improvement in that means (16) are provided for controlling the emitter current at the second node (2) in response to voltage on the first node (1) in order to inhibit saturation of the input transistors (QA, QB) and to enhance switching speed of the logic gate (14). The emitter current controlling means (16) may include a current regulating transistor (Q5) coupled between the second node (2) and a ground reference wherein the base electrode thereof is coupled through a third node (3) to a biasing means (RF) coupled to the first node. The current regulating transistor (Q5) may be a Schottky transistor, that is, a transistor with a Schottky diode (D1) coupled between the base electrode and the collector electrode. The biasing means may be a feedback resistor (RF) coupled between the first node (1) and the third node (3). Voltage across the feedback resistor (RF) may be clamped to limit voltage range.

公开(公告)号：EP0283680A3

公开(公告)日：1989-06-14

申请号：EP88101465.8

申请日：1988-02-02

申请人： International Business Machines Corporation

发明人： Braden, James J.

IPC分类号： H03K19/013

CPC分类号： H03K19/01806 ,  H03K19/00376 ,  H03K19/013

摘要： A non-saturating voltage output driver circuit in which a controlling mechanism (Q4, D1) is connected to a current source (22), a reference voltage (REF.OUT) and a load. A pre-driver (Q3) is also connected to the current source (22). Connected to the controlling mechanism (Q4, D1), the pre-driver (Q3) and the load is a down-level output driver (Q5), the output of which is dependent on the reference voltage (REF.OUT), but kept out of saturation and substantially constant over a temperature range.

公开(公告)号：EP0250947A3

公开(公告)日：1989-04-19

申请号：EP87108289.7

申请日：1987-06-09

申请人： MOTOROLA, INC.

发明人： McLaughlin, Kevin L.

IPC分类号： H03K19/094 ,  H03K19/013

CPC分类号： H03K19/09448

摘要： A BIMOS circuit is provided wherein an output terminal 14 is coupled between an upper NPN and a lower PNP pair of push-pull transistors 11, 12 for providing high current drive capability along with no d.c. power dissipation. A P-channel MOS transistor 16 is coupled between a node 17 and both the collector of the NPN transistor and a first supply voltage terminal for biasing the NPN transistor. An N-channel MOS transistor 18 is coupled between the node and both the collector of the PNP transistor and a second supply voltage terminal for biasing the PNP transistor. The gates of the MOS devices are connected to an input terminal 21. The node is further coupled to the bases of the NPN and PNP transistors and is coupled to the output terminal by a transmission gate 19 or a resistor 22 for increasing the output voltage swing.

公开(公告)号：EP0286808A2

公开(公告)日：1988-10-19

申请号：EP88102733.8

申请日：1988-02-24

申请人： International Business Machines Corporation

发明人： Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Skooglund, Daniel Edward

IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/003

CPC分类号： H03K19/01831 ,  H03K19/00353

摘要： Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differen­tial pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources. As the amplitude is decreased the input switching voltage decreases because the current through the devices decreases which results in smaller base-emitter and diode voltages. Due to the commonly controlled current sources, the predriver amplitude decreases as the driver amplitude decreases. The predriver is designed such that its variable output supplies the driver with the proper input switching voltage at any driver amplitude. This keeps the effective input transition time constant which results in constant output overshoot.

摘要翻译： 公开了一种用于减少和在高速驱动器保持恒定的过冲的方法和电路。 该电路包括预驱动器电路的所有被驱动单端形式和驱动器电路，其全部被差分由预驱动器输出驱动。 预驱动器和驱动器是差分对，与常用控制单独的晶体管的电流源。 二极管已在一系列被添加与差动对每个发射器。 肖特基二极管是由于它们的低电容的优选。 二极管增加输入切换电压（最小输入电压摆动thatwill导致输出到完全切换）的差动对，因为它们必须因此打开和关闭。所述增加导致在有效过渡时间增加了进行切换，这导致 较小的过冲，因为电路正在切换慢。 所述驱动器的输出振幅由它控制的常用控制电流源的电流源电流的电压设定。 作为振幅减小时，输入切换电压减小，因为通过设备跌幅，这导致更小的基极 - 发射极二极管和电压下的电流。 由于通常受控电流源，其幅度减小预驱动器作为驱动振幅减小。 预驱动器被设计检查做它的可变输出提供在任何驱动振幅适当的输入切换电压的驱动程序。 这样可以使有效投入转变的时间常数导致恒定的输出过冲。

公开(公告)号：EP0185673A4

公开(公告)日：1988-06-13

申请号：EP85901808

申请日：1985-03-19

申请人： ADVANCED MICRO DEVICES INC

发明人： MA BING-FONG

IPC分类号： H03K17/14 ,  H03K19/013 ,  H03K19/018 ,  H03K19/086 ,  H03K17/04

CPC分类号： H03K19/0136 ,  H03K19/086

公开(公告)号：EP0270296A2

公开(公告)日：1988-06-08

申请号：EP87310378.2

申请日：1987-11-25

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Suzuki, Hirokazu ,  Tahara, Akinori ,  Saito, Shinji

IPC分类号： H03K19/013

CPC分类号： H03K5/02 ,  H03K19/212

摘要： A semiconductor logic circuit comprises a clock driver circuit (21) and a clocked circuit (22) which carries out a clocked operation responsive to an output of the clock driver circuit, where an output logic amplitude (L 1 ) of the clock driver circuit is set to a value which is greater than an internal logic amplitude (L 2 ) of the clocked circuit and is less than or equal to four times the internal logic amplitude of the clocked circuit.

摘要翻译： 半导体逻辑电路包括响应于时钟驱动电路（21）的输出执行时钟控制的时钟驱动电路（21）和时钟电路（22），其中时钟驱动器的输出逻辑幅度（L1） 电路（21）被设置为大于时钟控制电路（22）的内部逻辑振幅（L2）的值，小于或等于时钟电路（22）的内部逻辑振幅（L2）的四倍， 。