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公开(公告)号：EP0162707A3
公开(公告)日：1987-10-07
申请号：EP85303591
申请日：1985-05-21
发明人： Bauer, Jerry R.
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F21/125 , G06F2221/0744 , G06F2221/2107
摘要： In order to protect, from unauthorised copying, computer code placed in internal circuitry in a computer, an encoding Exclusive-OR gate (23) is provided in the computer for each data transmission lead (8) from the respective circuitry. One input lead of each encoding Exclusive-OR gate is connected to the corresponding incoming data transmission lead (7) in order to receive data to be transmitted on accessible data lines. The other input lead of each encoding Exclusive-OR gate is connected via a code matrix (22) to a source (11) of a random M-bit binary number. The output signal provided by each Exclusive-OR gate (23) is the encoded data bit which Is applied to one of the accessible data lines (8). The encoded data is decoded by a circuit similar to the encoding circuit. In the decoding circuit a decoding Exclusive-OR gate (33) is provided for each data transmission lead (9). One input lead of each decoding Exclusive-OR gate (33) is connected to an incoming encoded data transmission lead (8). The other input lead to the decoding Exclusive-OR gate (33) is connected via a code matrix (32) which is similar to the code matrix (22) provided in the encoding circuit, to a source (II) of a random M-bit binary number, where the M-bit binary number is the same M-bit binary number provided in the encoding circuit. The output leads of the decoding Exclusive-OR gates (9) are the transmission lines which carry the decoded data. The encoding matrix (22, 32) and the random M-bit word are the same in the encoding and decoding circuit, so the data on the output leads of the Exclusive-OR gates is properly decoded. However, the data on bus lines running between integrated circuits, and which therefore may be intercepted through the use of logic probes, is in encoded form, thereby. substantially increasing the effort required to illicitly determine the data stored.
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42.发明公开
公开(公告)号：EP0219994A2
公开(公告)日：1987-04-29
申请号：EP86307481.1
申请日：1986-09-30
IPC分类号： G05F3/24
摘要： A temperature compensated complementary metal-insulator-semiconductor oscillator receives a temperature independent reference voltage from an external source. The temperature independent reference voltage is attenuated and summed with a threshold voltage in order to bias a gate electrode of MOSFET. A bipolar p-n junction diode is connected to the MOSFET at a source electrode in order to bias the MOSFET with a temperature dependent forward voltage drop to compensate for temperature variations therein. The MOSFET controls a temperature independent current. A current mirror assembly receives the current and controls a Schmitt trigger oscillator. The Schmitt trigger oscillator generates a signal having a temperature independent constant period.
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公开(公告)号：EP0162521A3
公开(公告)日：1986-10-08
申请号：EP85200770
申请日：1985-05-14
发明人： Cooley, Richard F.
CPC分类号： H01L23/49827 , H01L23/057 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/10161 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/16195 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A programmable package for integrated circuits includes a ground plane, a power plane and a plurality of electrically isolated but conductive fingers and a multiplicity ofterminals on the exterior of the package. A selected number of fingers handling selected I/O signals are connected directly to the multiplicity of terminals on the package exterior. Additional fingers are available within the package connected to a ground plane or to a power plane or to an I/0 plane. The result is a package in which the particular terminals connected to external power and ground and handling I/O signals can be programmed in accordance with the needs of the circuit and the arrangement of the bonding pads on the die.
摘要翻译： 用于集成电路的可编程封装包括接地平面，电源平面和多个电隔离但导电的指状物以及封装外部的多个端子。 处理所选I / O信号的选定数量的手指直接连接到外包装上的多个终端。 附加的手指在连接到接地平面或电源平面或I / O平面的封装内可用。 结果是其中可以根据电路的需要和芯片上的焊盘的布置编程连接到外部电源和接地和处理I / O信号的特定端子的封装。
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44.发明公开Multiplier circuitry using pass transistors and method of constructing same 失效Multipliziererschaltung mit Passiertransistoren und Konstruktionsverfahren derselben。
公开(公告)号：EP0179568A1
公开(公告)日：1986-04-30
申请号：EP85306733.8
申请日：1985-09-23
IPC分类号： G06F7/52
CPC分类号： G06F7/5306 , G06F2207/4816
摘要： PASS transistors are used to reduce the layout complexity of multiplication circuitry by using PASS transistors connected to pass a first and second input function to an output node in response to a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor, thereby to generate an output function related to the input function.
摘要翻译： PASS晶体管用于通过使用连接的PASS晶体管来响应于输出节点上的所选择的输出功能而将第一和第二输入功能传递到输出节点来降低乘法电路的布局复杂性。 PASS晶体管包括能够响应于施加到晶体管的CONTROL信号而传递输入功能的晶体管，从而产生与输入功能相关的输出功能。
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公开(公告)号：EP0155041A2
公开(公告)日：1985-09-18
申请号：EP85200265.8
申请日：1985-02-27
发明人： Haque, Yusuf A.
IPC分类号： H03K5/00
CPC分类号： H03K5/00006 , H03K5/1565
摘要： A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50 %, or any other predefined value.
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公开(公告)号：EP0145101A2
公开(公告)日：1985-06-19
申请号：EP84201817.8
申请日：1984-12-06
发明人： Haque, Yusuf A.
IPC分类号： H04L27/14
CPC分类号： H04L27/1563 , H04L1/206
摘要： A carrier detection circuit includes a rectification stage, an integrator, a comparator, and a digital counter. By utilizing a digital counter, long time constants are provided without the use of external components. If desired, a mark detect circuit is used when a mark must be present to signify the presence of carrier. Hystersis is provided by the comparator to insure that slight fluctuations in the carrier level do not affect the comparison.
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公开(公告)号：EP0138260A2
公开(公告)日：1985-04-24
申请号：EP84201369.0
申请日：1984-09-25
发明人： Gregorian, Roubik , Fotouhi, Bahram
摘要： A novel switched capacitor gain stage uses a unique circuit design and clocking technique that reduces the component mismatch offset voltage and the clock-induced feedthrough offset voltage produced by the circuit. The totalcapac- itance ratio between the input capacitors and the feedback capacitor necessary to achieve a desired total gain is also minimized.
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48.发明授权Switched capacitor comparator and method for eliminating the effects of inherent offset voltages when using, as a comparator, an opamp 失效切换电容器比较器和用于消除作为比较器，运算放大器的静态偏置电压的影响的方法
公开(公告)号：EP0049024B1
公开(公告)日：1985-02-27
申请号：EP81201081.7
申请日：1981-09-29
发明人： Haque, Yusuf A.
CPC分类号： G01R17/00 , H03F3/45753 , H03K5/2481 , H03K5/249
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公开(公告)号：EP0109853A2
公开(公告)日：1984-05-30
申请号：EP83307114.5
申请日：1983-11-21
发明人： Batra, Tarsaim Lal
CPC分类号： H01L27/112 , H01L27/115
摘要： An array of MOS transistors (30) formed in a semiconductor substrate having a plurality of continuous diffused lines (bit lines) (7-3, 7-4, 7-5 and 7-6) serving as the source and drain regions of a plurality of MOS transistors. A plurality of conductive word lines (33, 133) are formed over the plurality of diffused lines, crossing the diffused lines at substantially right angles, with each conductive word line serving as the gates of a plurality of MOS transistors. Each transistor of the memory array is formed in a region containing two continuous diffused lines and a single word line. A single electrical contact (36-3, 4, 5, 6) to a bit line is formed for each such diffused line.
摘要翻译： 在具有多个连续扩散线（位线）（7-3,7-4,7-5和7-6）的半导体衬底中形成的MOS晶体管（30）的阵列（7-3,7-4,7-5和7-6）用作a 多个MOS晶体管。 多条导电字线（33,133）形成在多条扩散线上，以基本上直角与扩散线交叉，每条导电字线用作多个MOS晶体管的栅极。 存储器阵列的每个晶体管形成在包含两条连续扩散线和单条字线的区域中。 对于每条这样的扩散线形成到位线的单个电触点（36-3,4,5,6）。
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公开(公告)号：EP0094143A1
公开(公告)日：1983-11-16
申请号：EP83301231.3
申请日：1983-03-08
发明人： Barlow, Allen R. , Petersen, Corey
CPC分类号： H01L27/11898 , H03F3/42 , H03K19/018521 , H03K19/09448 , H03K19/0948
摘要： A CMOS push-pull output buffer (171) ist constructed with a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors when the N channel transistors are turned off.
In another embodiment, selected ones of the N channel and P channel transistors are formed to have a high drain to bulk breakdown voltage.
In another embodiment, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage, thus providing a first stage which drives a second stage having a plurality of P channel transistors and a plurality of N channel transistors which provide the high voltage output voltage.
In another embodiment, the first stage is driven by a single-ended control voltage and serves to drive a second stage comprising a plurality of N channel transistors and a plurality of bipolar transistors, whereby said second stage provides the high voltage output signal.
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