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公开(公告)号：EP4207571A1
公开(公告)日：2023-07-05
申请号：EP22213961.0
申请日：2022-12-15
Applicant: STMicroelectronics S.r.l.
Inventor： BARBIERI, Andrea , VIDONI, Aldo , ZAMPROGNO, Marco
Abstract: A DC-DC boost converter includes an inductor (L) coupled between an input voltage (Vin) and an input node (Nn), a diode (D1) coupled between the input node and an output node (No), and an output capacitor (C1) coupled between the output node and ground such that an output voltage (VBOOST) is formed across the output capacitor. A switch (Sw) selectively couples the input node to ground in response to a drive signal (Vdrive). Control loop circuitry (Vfbk, 15') includes an error amplifier (17') to generate an analog error voltage (Verr) based upon a comparison of a feedback voltage (Vfbk) to a reference voltage (Vref), the feedback voltage being indicative of the output voltage, a quantizer (21) to quantize the analog error voltage to produce a digital error signal (Err), and a drive voltage generation circuit (22) to generate the drive signal as having a duty cycle based upon the digital error signal.
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42.发明公开
公开(公告)号：EP4068351A3
公开(公告)日：2023-06-07
申请号：EP22165630.9
申请日：2022-03-30
Applicant: STMicroelectronics S.r.l.
Inventor： MINOTTI, Agatino
Abstract: A connecting strip (50) of conductive elastic material having an arched shape having a concave side (50A) and a convex side (50B). The connecting strip is fixed at the ends to a support carrying a die (72, 73) with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die (72, 73), thus electrically connecting the at least one die (72, 73) to the support (70).
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43.发明公开
公开(公告)号：EP4187540A1
公开(公告)日：2023-05-31
申请号：EP22209608.3
申请日：2022-11-25
Applicant: STMicroelectronics S.r.l.
Inventor： PETRONI, Elisa , REDAELLI, Andrea
Abstract: A phase change memory element (10, 10'; 10") has a memory region (12), a first electrode (13) and a second electrode (14). The memory region (12) is arranged between the first and the second electrodes (13, 14) and have a bulk zone (12B) and an active zone (12A). The memory region (12) is a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone (12B) of the memory region (12). The active zone (12A) is configured to switch between a first stable state associated to a first memory logic level and a second stable state associated to a second memory logic level. The active zone (12A) has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion (31), having a first stoichiometry, and a second portion (32), having a second stoichiometry, different from the first stoichiometry.
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44.发明公开
公开(公告)号：EP4177960A1
公开(公告)日：2023-05-10
申请号：EP22204133.7
申请日：2022-10-27
Applicant: STMicroelectronics S.r.l.
Inventor： CASCINO, Salvatore , GUARNERA, Alfio , SAGGIO, Mario Giuseppe
IPC: H01L29/78 , H01L21/336 , H01L29/06
Abstract: A semiconductor power device has a maximum nominal voltage and includes: a first conduction terminal (1a) and a second conduction terminal (lb); a semiconductor body (2), containing silicon carbide and having a first conductivity type; body wells (7) having a second conductivity type, housed in the semiconductor body and separated from one another by a body distance (LB); source regions housed in the body wells (7); and floating pockets (20) having the second conductivity type, formed in the semiconductor body (2) at a distance from the body wells (7) between a first face (2a) and a second face (2b) of the semiconductor body (2). The floating pockets (20) are shaped and arranged relative to the body wells (7) so that a maximum intensity of electrical field around the floating pockets (20) is greater than a maximum intensity of electrical field around the body wells (7) at least for values of an operating voltage (VDS) between the first conduction terminal (1a) and the second conduction terminal (1b) greater than a threshold voltage, the threshold voltage being less than the maximum nominal voltage.
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45.发明公开
公开(公告)号：EP4173715A1
公开(公告)日：2023-05-03
申请号：EP22199518.6
申请日：2022-10-04
Applicant: STMicroelectronics S.r.l.
Inventor： RAIA, Lillo , FREGUGLIA, Alessandro , PESATURO, Massimiliano
Abstract: A chip (1) for biochemical reactions comprising: a first body (3) including a plurality of first through openings (5) arranged according to an arrangement pattern; a second body (4), having a hydrophilic surface (8), coupled to the first body (3) on the hydrophilic surface (8); and an intermediate layer (10), which extends over the hydrophilic surface (8) and forms a coupling interface between the first and the second bodies. The intermediate layer (10) is of hydrophobic material, extends continuously over the hydrophilic surface, and has a plurality of second through openings (12) through which respective regions (8') of the hydrophilic surface (8) are exposed. The hydrophilic regions (8') may be functionalized for carrying out a PCR.
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Patent Agency Ranking
公开(公告)号：EP4137366A3
公开(公告)日：2023-05-03
申请号：EP22190946.8
申请日：2022-08-18
Applicant: STMicroelectronics S.r.l.
Inventor： ARGENTO, Davide , PENNISI, Orazio , CASTORINA, Stefano , POLETTO, Vanni , LANDINI, Matteo , MAINO, Andrea
IPC: B60R21/017 , G01R27/26 , G01R31/00 , G01R31/64 , B60R21/01
Abstract: A system and method for measuring a capacitance value of a capacitor (102) are provided. In embodiments, a resistor (112) is coupled to a terminal of the capacitor (102). A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor (102) is measured. The discharge routine includes sinking a current through a discharge circuit (108, 110) coupled to the resistor (112) from first to second. Integration of a difference in voltage at terminals of the resistor (112) during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor (112). The health of the capacitor (102) is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：EP4170730A1
公开(公告)日：2023-04-26
申请号：EP22201739.4
申请日：2022-10-14
Inventor： GERMANA-CARPINETO, Rosalia , MASOERO, Lia , INNACOLO, Luigi
IPC: H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08
Abstract: La présente description concerne un dispositif électronique (100) comprenant un substrat semiconducteur (102) et des transistors dont les grilles (120) sont contenues dans des tranchées (110) s'étendant dans le substrat semiconducteur, chaque transistor comprenant un caisson semiconducteur (130) dopé d'un premier type de conductivité, le caisson étant enterré dans le substrat semiconducteur et au contact de deux tranchées adjacentes parmi lesdites tranchées, une première région semiconductrice (152) dopée d'un deuxième type de conductivité, recouvrant le caisson, au contact du caisson, et au contact des deux tranchées adjacentes, une deuxième région semiconductrice (150) dopée du deuxième type de conductivité plus fortement dopée que la première région semiconductrice, s'étendant dans la première région semiconductrice, et une troisième région semiconductrice (132) dopée du premier type de conductivité, plus fortement dopée que le caisson, recouvrant le caisson, au contact de la première région, et s'étendant dans le substrat semiconducteur au contact du caisson.
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公开(公告)号：EP4170461A1
公开(公告)日：2023-04-26
申请号：EP22201942.4
申请日：2022-10-17
Applicant: STMicroelectronics S.r.l.
Inventor： RIVOLTA, Stefano Paolo , MURA, Roberto , BRACCO, Lorenzo , RIZZARDINI, Federico
IPC: G06F1/16
Abstract: Detection method (50) of a first or second state of a foldable electronic device (10) comprising a first and a second hardware element (12; 14) tiltable to each other and accommodating a first and a second electrode (20b; 22b) which are in contact with each other when the foldable electronic device is in the first state and at a distance from each other otherwise. The detection method (50) is performed by a control unit (23) of the foldable electronic device and comprises the steps of: acquiring (S10) a first and a second charge variation signal indicative of environmental electric/electrostatic charge variations detected by the first and second electrodes; generating (S12) a differential signal (S D ) indicative of a difference between the first (S Q1 ) and the second (S Q2 ) charge variation signals; generating (S14, S16, S18, S20), as a function of the differential signal (S D ), one or more feature signals (S T ); and generating (S22), as a function of the one or more feature signals (S T ), a contact signal (Sc) indicative of the first or second states of the foldable electronic device (10) .
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公开(公告)号：EP4148492A1
公开(公告)日：2023-03-15
申请号：EP22193906.9
申请日：2022-09-05
Applicant: STMicroelectronics S.r.l.
Inventor： FINCATO, Antonio
Abstract: An optical beam steering device (100) and a method for beam steering are described. The optical beam steering device including: a laser source (102) coupled to an optical phased array, OPA. The OPA includes: a beam splitter network (103) optically coupled to the laser source and configured to split a laser beam generated by the laser source into N outputs to generate an output optical beam; a first network of first phase shifters (110) configured to steer the output optical beam in a first direction away from a longitude direction; and a second network of second phase shifters (112) configured to steer the output optical beam in a second direction away from the longitude direction, the second direction being opposite to the first direction.
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公开(公告)号：EP4148382A1
公开(公告)日：2023-03-15
申请号：EP22191021.9
申请日：2022-08-18
Applicant: STMicroelectronics S.r.l.
Inventor： GUERINONI, Luca , GATTERE, Gabriele
IPC: G01C19/5649 , G01C25/00
Abstract: A gyroscopic sensor unit (101) detects a phase drift between a demodulated output signal and a demodulation signal during output of a quadrature test signal. A delay calculator (116) detects the phase drift based on changes in the demodulated output signal during application of the quadrature test signal. A delay compensation circuit (118) compensates for the phase drift by delaying the demodulation signal by the phase drift value.
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