公开(公告)号：EP2016590A2

公开(公告)日：2009-01-21

申请号：EP07783139.4

申请日：2007-05-02

申请人： SanDisk Corporation

发明人： LI, Yan

IPC分类号： G11C16/26 ,  G11C11/56 ,  G11C7/22

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2207/107 ,  G11C2207/2245 ,  G11C2207/2281

摘要： Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A scheme for caching read data is implemented so that even when the read for a current page on a current wordline must be preceded by a prerequisite read of data on an adjacent wordline, the prerequisite read along with any I/O access is preemptively done in the cycle for reading a previous page so that the current read can be performed while the previously read page is busy with the I/O access.

公开(公告)号：EP1864289A1

公开(公告)日：2007-12-12

申请号：EP06739812.3

申请日：2006-03-27

申请人： SanDisk Corporation

发明人： LI, Yan ,  YERO, Emilio

IPC分类号： G11C7/00 ,  G11C16/10

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

公开(公告)号：EP1535285B1

公开(公告)日：2006-03-22

申请号：EP03794474.1

申请日：2003-08-13

申请人： SanDisk Corporation

发明人： CERNEA, Raul-Adrian ,  QUADER, Khandker, N. ,  LI, Yan ,  CHEN, Jian ,  FONG, Yupin

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

公开(公告)号：EP2186094B1

公开(公告)日：2012-03-14

申请号：EP08830722.8

申请日：2008-08-20

申请人： Sandisk Corporation

发明人： LI, Yan ,  FONG, Yupin, Kawing ,  MOKHLESI, Nima

IPC分类号： G11C7/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5647

摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

公开(公告)号：EP1599881B1

公开(公告)日：2010-12-29

申请号：EP04708564.2

申请日：2004-02-05

申请人： SanDisk Corporation

发明人： LUTZE, Jeffrey, W. ,  CHEN, Jian ,  LI, Yan ,  HIGASHITANI, Masaaki

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

公开(公告)号：EP2191475A2

公开(公告)日：2010-06-02

申请号：EP08831318.4

申请日：2008-09-02

申请人： Sandisk Corporation

发明人： LI, Yan

IPC分类号： G11C16/34

CPC分类号： G11C8/10 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3454

摘要： Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.

公开(公告)号：EP1864289B1

公开(公告)日：2010-02-17

申请号：EP06739812.3

申请日：2006-03-27

申请人： SanDisk Corporation

发明人： LI, Yan ,  YERO, Emilio

IPC分类号： G11C7/00 ,  G11C16/10

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

公开(公告)号：EP1869681B1

公开(公告)日：2009-08-19

申请号：EP06739682.0

申请日：2006-03-27

申请人： SanDisk Corporation

发明人： LI, Yan ,  CERNEA, Raul-Adrian

IPC分类号： G11C16/34

CPC分类号： G11C16/3468

摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

公开(公告)号：EP2074626A2

公开(公告)日：2009-07-01

申请号：EP07841761.5

申请日：2007-08-31

申请人： Sandisk Corporation

发明人： TU, Loc ,  HOOK, Charles Moana ,  LI, Yan

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

公开(公告)号：EP2062265A2

公开(公告)日：2009-05-27

申请号：EP07814597.6

申请日：2007-08-30

申请人： Sandisk Corporation

发明人： LI, Yan ,  TU, Loc ,  HOOK, Charles Moana

IPC分类号： G11C16/10 ,  G11C29/50

CPC分类号： G11C16/3454 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3481 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004

摘要： High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.