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公开(公告)号：EP2858248A1
公开(公告)日：2015-04-08
申请号：EP14186401.7
申请日：2014-09-25
申请人： Analog Devices, Inc.
发明人： Shen, Junhua , Kapusta, Ronald A.
CPC分类号： H03M1/0854 , H03M1/04 , H03M1/0697 , H03M1/46 , H03M1/462
摘要： Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
摘要翻译： 本发明的实施例可以提供精度增强技术来提高ADC SNR。 例如，可以执行从最高有效位（MSB）到数字字的预定的较低有效位和额外的位试验的规则位测试。 可以组合正常和额外的比特试验的结果以产生数字输出信号。 可以测量残留误差，并且可以基于测量的残余误差来调整数字输出信号。
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42.发明公开Signal processing device and signal processing method 审中-公开Signalverarbeitungsschaltung和Signalverarbeitungsverfahren
公开(公告)号：EP2852062A2
公开(公告)日：2015-03-25
申请号：EP14184229.4
申请日：2014-09-10
摘要： According to an embodiment, a signal processing device includes an integrator, a first analog-to-digital converter, and a histogram creator. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The first analog-to-digital converter is configured to perform an analog-to-digital conversion operation that generates digital data of the electrical charge using an integration output from the integrator, on a parallel with an integration operation performed by the integrator. The histogram creator is configured to create a histogram that represents an energy distribution of the electromagnetic waves, from the digital data generated by the first analog-to-digital converter.
摘要翻译： 根据实施例，信号处理装置包括积分器，第一模数转换器和直方图创建器。 积分器被配置为集成对应于电磁波的电荷。 第一模数转换器被配置为执行使用来自积分器的积分输出的并且与积分器执行的积分操作并行地生成电荷的数字数据的模数转换操作。 直方图创建器被配置为从由第一模数转换器产生的数字数据创建表示电磁波的能量分布的直方图。
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43.发明公开Background calibration of adc reference voltage errors due to input signal dependency 审中-公开背景校准根据在A / D转换器的基准电压的误差所造成的输入信号
公开(公告)号：EP2779463A3
公开(公告)日：2014-12-10
申请号：EP14157547.2
申请日：2014-03-03
申请人： Analog Devices, Inc.
CPC分类号： H03M1/38 , H03M1/1019 , H03M1/164 , H03M1/44 , H03M1/46
摘要： Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.
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公开(公告)号：EP2662983A1
公开(公告)日：2013-11-13
申请号：EP12167372.7
申请日：2012-05-09
申请人： NXP B.V.
CPC分类号： H03M1/0614 , H03M1/1014 , H03M1/1215 , H03M1/46
摘要： An analogue-to-digital converter, ADC, for converting an analogue input signal (Vin) into a digital signal (output) is disclosed. The ADC comprises a correction unit (15) adapted to generate a correction signal, which offsets the output signal from a feedback DAC configured to produce an analogue representation of the digital signal (output) so that the offset output signal (Vdac) has the same common-mode or bias point as the input signal (Vin).
摘要翻译： 公开了一种用于将模拟输入信号（Vin）转换为数字信号（输出）的模拟 - 数字转换器ADC。 ADC包括校正单元（15），该校正单元（15）适于产生校正信号，其校正来自被配置为产生数字信号（输出）的模拟表示的反馈DAC的输出信号，使得偏移输出信号（Vdac）具有相同的 共模或偏置点作为输入信号（Vin）。
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45.发明公开
公开(公告)号：EP2221974A2
公开(公告)日：2010-08-25
申请号：EP10153869.2
申请日：2010-02-17
申请人： Number 14 B.V.
CPC分类号： H03F3/45753 , H03M1/0692 , H03M1/46 , H03M1/745
摘要： Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.
摘要翻译： 具有上电修整的放大器和使用具有放大器系统输入的放大器系统和放大器系统输出的方法，放大器，比较器，具有耦合到比较器的输出的输入的逐次逼近寄存器，用于切换 从放大器系统输入的放大器输入以使放大器输入短路;第二开关，用于将放大器的输出从放大器系统输出切换到比较器的输入;逐次逼近寄存器的输出耦合到N位 数模转换器，D / A转换器是对至少最高有效位使用小于2的基数的非二进制转换器，并且D / A转换器的输出端耦合到放大器 以控制放大器的输入偏移。 公开了用于放大器，比较器和D / A转换器的新颖实施例。
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公开(公告)号：EP2146435A3
公开(公告)日：2010-08-11
申请号：EP09173127.3
申请日：2007-11-30
发明人： Dosho, Shiro , Morie, Takashi , Matsukawa, Kazuo
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： An A-to-D converter comprising a plurality of successive approximation type A-to-D converters, each of which includes a cyclic D-to-A converter, a comparator for comparing the analog value with an output value of the D-to-A converter and memory means for sequentially storing an output value of the comparator and supplying the stored value to the D-to-A converter in a reverse order; a plurality of sample and hold circuits for supplying an analog value to each of the plurality of successive approximation type A-to-D converters; and a multiplexer for sequentially supplying an input analog signal to the plurality of sample and hold circuits. Flip-flops included in the respective memory means of the plurality of successive approximation type A-to-D converters for storing an output value of the respective comparator are connected together to form a shift register.
摘要翻译： 一种A / D转换器，包括多个逐次逼近型A / D转换器，每个转换器包括循环D / A转换器，比较器，用于将模拟值与D转换器的输出值进行比较 -A转换器和存储器装置，用于顺序地存储比较器的输出值并将存储的值以相反的顺序提供给D至A转换器; 多个采样和保持电路，用于向所述多个逐次逼近型A / D转换器中的每一个提供模拟值; 以及多路复用器，用于向多个采样和保持电路顺序地提供输入模拟信号。 包括在用于存储相应比较器的输出值的多个逐次逼近型A / D转换器的相应存储器装置中的触发器连接在一起以形成移位寄存器。
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47.发明授权SIGNAL CONDITIONING CIRCUIT INCLUDING A COMBINED ADC/DAC, SENSOR SYSTEM, AND METHOD THEREFOR 无效期组合ADC / DAC转换器，传感器系统及其方法信号调理电路
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公开(公告)号：EP2146435A2
公开(公告)日：2010-01-20
申请号：EP09173127.3
申请日：2007-11-30
发明人： Dosho, Shiro , Morie, Takashi , Matsukawa, Kazuo
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter ( 11 ), a comparator ( 12 ) for comparing an analog value with an output value of the D-to-A converter ( 11 ), and memory means ( 13 ) for sequentially storing an output value of the comparator ( 12 ) and supplying the stored value to the D-to-A converter ( 11 ) in a reverse order.
摘要翻译： 一种A到D转换器，包括多个逐次逼近型A到D转换器，每个转换器包括循环D转换器，比较器，用于将模拟值与D转换器的输出值进行比较 -A转换器和存储器装置，用于顺序地存储比较器的输出值，并以相反的顺序将所存储的值提供给D-A转换器; 多个采样和保持电路，用于向多个逐次逼近型A-D转换器中的每一个提供模拟值; 以及多路复用器，用于向多个采样和保持电路顺序地提供输入模拟信号。 包括在用于存储各个比较器的输出值的多个逐次逼近型A-D转换器的相应存储器装置中的触发器连接在一起以形成移位寄存器。
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公开(公告)号：EP1687900A1
公开(公告)日：2006-08-09
申请号：EP04820015.8
申请日：2004-11-10
申请人： Analog Devices, Inc.
IPC分类号： H03M1/00
CPC分类号： H03M1/004 , G06F1/3209 , H03M1/002 , H03M1/46 , H03M1/462 , H03M1/70 , H04W52/0287 , Y02D70/122
摘要： A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.
摘要翻译： 一种用于将设备放置在所选择的操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，在第二逻辑状态下断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的操作模式的装置，发生在逻辑 状态转换在设备选择输入。 所选择的操作模式可以是诸如菊花链操作模式的减小的功耗模式，例如或设备的另一操作模式，或者适应模拟输入范围的编程的模式。
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50.发明公开Analog-digital converter and method for converting data of the same 审中-公开Schaltungsanordnung und Verfahren zur Analog-Digital Konvertierung
公开(公告)号：EP1341312A1
公开(公告)日：2003-09-03
申请号：EP03004090.1
申请日：2003-02-25
发明人： Yoshinaga, Chikashi
IPC分类号： H03M1/46
CPC分类号： H03M1/1023 , H03M1/1225 , H03M1/46
摘要： An analog-digital converter has a sampling capacitor in which a voltage of an analog input terminal is sampled, and a digital-analog converter for performing an electric discharge of a residual voltage of the sampling capacitor at a timing prior or subsequent to an analog-digital conversion.
摘要翻译： 模拟数字转换器具有对模拟输入端子的电压进行采样的采样电容器，以及用于在模拟数字转换器之前或之后的时刻对采样电容器的残余电压进行放电的数模转换器， 数字转换。
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