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1.发明公开SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER APPLYING CALIBRATION CIRCUIT, ASSOCIATED CALIBRATING METHOD, AND ASSOCIATED ELECTRONIC DEVICE 审中-公开适用的近似寄存器模拟数字转换器应用校准电路，相关的校准方法和相关的电子设备
公开(公告)号：EP3200352A1
公开(公告)日：2017-08-02
申请号：EP17151197.5
申请日：2017-01-12
申请人： MediaTek Inc.
发明人： LIU, Chun-Cheng
CPC分类号： H03M1/1009 , H03M1/001 , H03M1/0692 , H03M1/1042 , H03M1/164 , H03M1/38 , H03M1/468
摘要： A Successive Approximation Register Analog-to-Digital Converter including: a comparing module (170) and a calibration circuit (160). The comparing module (170) is arranged to generate a first comparison result by comparing an input voltage value (V in' ) of the SAR ADC (100) with a first voltage value (V cm +V delta ) and a second result by comparing the input voltage value with a second voltage value (V cm -V delta ); the calibration circuit (160) coupled to the comparing module (170) is for generating a determination result determining whether the input voltage value (V in' ) is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.
摘要翻译： 逐次逼近寄存器模数转换器包括：比较模块（170）和校准电路（160）。 比较模块（170）被配置为通过将SAR ADC（100）的输入电压值（Vin'）与第一电压值（Vcm + Vdelta）进行比较来产生第一比较结果，并且通过比较输入电压 值与第二电压值（Vcm-Vdelta）; 耦合到比较模块（170）的校准电路（160）用于根据第一比较结果和第二比较结果产生确定输入电压值（Vin'）是否在范围内的确定结果，并且输入校准 模式根据确定结果。
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2.发明公开METHOD AND APPARATUS FOR CONVERSION OF VALUE OF ANALOG SIGNAL TO COMPRESSED DIGITAL WORD 审中-公开方法和设备中，用于模拟信号的值转换成压缩的数字字转换
公开(公告)号：EP3142256A1
公开(公告)日：2017-03-15
申请号：EP15200947.8
申请日：2015-12-17
IPC分类号： H03M1/46
摘要： Method for conversion of a value of an analog signal to a compressed digital word (CW) uses conversion of the analog signal to a linear digital word (LW) according to a successive approximation scheme. The process of conversion of the analog signal to the linear digital word (LW) is terminated by the compression module (CPM) when all bits of the compression word (CW) have been already evaluated.
Apparatus for conversion of a value of an analog signal to a compressed digital word a linear successive approximation analog-to-digital converter (SA-ADC). The output of the linear digital word (LW) of this converter is connected to the input of the linear digital word (LW) of the compression module (CPM) comprising a section number register (RegS), while complete conversion signal output (End) of the compression module (CPM) is connected to a complete conversion signal input (End) of the linear analog-to-digital converter (SA-ADC), and a bit ready signal output (BitRdy) of the linear analog-to-digital converter (SA-ADC) is connected to a bit ready signal input (BitRdy) of the compression module (CPM).摘要翻译： 用于将模拟信号与一个压缩的数字字（CW）的值的转换方法使用模拟信号转换为线性数字字（LW）雅丁到逐次逼近方案。 该模拟信号到线性数字字（LW）的转化过程是由当压缩字（CW）的所有比特已经havebeen评估的压缩模块（CPM）终止。 装置用于将模拟信号的值转换成一个线性逐次逼近模拟 - 数字转换器（ADC SA）一个压缩的数字字。 线性数字字的这种转换器的输出（LW）被连接到包括段数寄存器（REG）中的线性数字字压缩模块的（LW）（CPM）的输入端，而完整的转换信号输出（完） 压制模块的（CPM）连接到线性模拟数字转换器（SA-ADC）的一个完整的转换信号输入（端），和线性模拟到数字的比特就绪信号输出（BitRdy） 转换器（SA-ADC）被连接到所述压缩模块（CPM）的位就绪信号输入端（BitRdy）。
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3.发明公开METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD USING SUCCESSIVE APPROXIMATION SCHEME 审中-公开方法和设备的时间间隔在数字WORD通过方案循序渐进的方法的折算
公开(公告)号：EP3141968A1
公开(公告)日：2017-03-15
申请号：EP15200980.9
申请日：2015-12-17
IPC分类号： G04F10/00
CPC分类号： G04F10/005 , H03M1/38
摘要： A method for conversion of a time interval to a digital word using a successive approximation scheme characterized in that the time interval (T) is mapped to a difference of a length of a reference time (RT) and a length of a signal time (ST). The reference time (RT) is generated from an instant (t 1 ) when the beginning of the time interval (T) is detected, and the signal time (ST) is generated from an instant (t 2 ) when the end of the time interval (T) is detected by the use the control module (CM). The generation of the reference time (RT) and the signal time (ST) is terminated at the same instant (t 3 ).
An apparatus for conversion of a time interval to a digital word using a successive approximation scheme comprises a control module (CM), two comparators (K R , K S ), two current sources (I R , I S ), two rails (R, S) and a set of capacitors (CS). The apparatus is characterized in that bottom plates of capacitors (C n-1 , C n-2 , ..., C 1 , C 0 ) of the set of capacitors (CS) are connected to a ground of the circuit, and top plates of these capacitors are connected respectively to moving contacts of change-over switches (S n-1 , S n-2 , ..., S 1 , S 0 ). First stationary contacts are connected to the signal rail (S), second stationary contacts are connected to the ground of the circuit, and third stationary contacts are connected to the reference rail (R).摘要翻译： 一种用于使用在做的时间间隔（T），其特征逐次逼近方案的时间间隔到的数字字的转换方法映射到的参考时间（RT）和的信号时间的长度的长度的差（ST ）。 从在时刻（T 1）中产生的基准时间（RT）当检测到的时间间隔（T）的开始，并且从在时刻产生的信号 - 时间（ST）（T 2）的时间。当端 间隔（T）是通过使用控制模块（CM）来检测。 的基准时间（RT）和所述信号 - 时间（ST）的产生在同一时刻（T 3）被终止。 的时间间隔，以使用逐次近似方案的数字字的转换的装置包括：控制模块（CM），两个比较器（KR，KS），两个电流源（IR，IS），两个轨道（R，S）和 一组电容器（CS）。 该装置的特征DASS电容器的底板（C N-1，C N-2，...，C 1，C 0）的组电容器（CS）被连接到电路的地，并且顶部的 论文电容器的板分别连接到移动切换开关的触点（S n-1个，S N-2，...，S 1，S 0）。 第一固定触点连接到所述信号轨道（S），第二固定触点连接到电路的接地，和第三固定触点被连接到基准轨道（R）。
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4.发明公开REFERENCE VOLTAGE GENERATOR FOR AN ANALOG-DIGITAL CONVERTER AND METHOD FOR ANALOG-DIGITAL CONVERSION 审中-公开REFERENZSPANNUNGSGENERATORFÜREINE模拟数字万用表SOWIE VERFAHREN ZUR ANALOG-DIGITAL-UMWANDLUNG
公开(公告)号：EP3138202A1
公开(公告)日：2017-03-08
申请号：EP14729141.3
申请日：2014-04-29
申请人： Synopsys, Inc.
IPC分类号： H03M1/46
CPC分类号： H03M1/38 , H03M1/0617 , H03M1/1245 , H03M1/468
摘要： Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.
摘要翻译： 模拟数字转换器被配置为将由一对输入电位表示的输入电压转换成使用逐次逼近的二进制代码。 模拟数字转换器包括提供第一对参考电位的参考电压发生器（RVG）和第二对参考电位。 模拟数字转换器还包括被配置为接收第一和第二对参考电位的开关电容器阵列（SCA）以及耦合到开关电容器阵列（SCA）的控制单元（CTRL），并且被配置为将 所述开关电容器阵列（SCA）根据所述转换的进展而到达所述第一对参考电位或所述第二对参考电位。
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5.发明公开VOLTAGE DOUBLING CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER (ADC) 审中-公开EANEN模拟数字万用表（ADC）SPANUNGSVERDOPPLUNGSSCHALTUNGFÜR
公开(公告)号：EP3111558A1
公开(公告)日：2017-01-04
申请号：EP15706980.8
申请日：2015-02-09
CPC分类号： H03M1/1245 , H03M1/0682 , H03M1/38 , H03M1/403 , H03M1/468 , H03M1/66
摘要： In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.
摘要翻译： 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。
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公开(公告)号：EP3095194A1
公开(公告)日：2016-11-23
申请号：EP14879162.7
申请日：2014-12-03
CPC分类号： H03M1/1245 , H03M1/0624 , H03M1/1009 , H03M1/1265 , H03M1/38 , H03M1/46
摘要： A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal. The cognitive network is adapted to receive the digital converted signal of the analog-to-digital converter, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.
摘要翻译： 公开了一种通过模拟信号输入端口连接到模拟信号源并适于产生基于经由模拟信号输入端口接收的模拟输入信号的数字输出信号的认知信号转换器。 认知信号转换器包括模数转换器和认知网络。 模拟 - 数字转换器适于基于模拟输入信号，采样时钟信号和处理时钟信号，通过根据采样时钟信号对模拟输入信号进行采样并量化每个模拟输入信号来产生数字转换信号 样本，其中量化处理由处理时钟信号操作。 认知网络适于接收模拟 - 数字转换器的数字转换信号，基于接收的数字转换信号和模拟信号的一个或多个特性来控制采样时钟信号和处理时钟信号中的至少一个 源，并且基于接收到的数字转换信号产生数字输出信号。 还公开了相应的集成电路，电子设备和方法。
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7.发明公开
公开(公告)号：EP3059857A1
公开(公告)日：2016-08-24
申请号：EP15155327.8
申请日：2015-02-17
申请人： NXP B.V.
CPC分类号： G04F10/005 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03L7/085 , H03L7/0992 , H03L7/1974 , H03L7/1976 , H03M1/38
摘要： A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.
摘要翻译： 公开了一种数字转换器（10）。 数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分电容器（24,25）上的电荷进行积分， ，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分器电容器（24,25）上的电荷来相对于参考电压来确定积分器输出电压（115），以便将积分器输出电压（115）降低到内部 通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。 公开了一种包括时间数字转换器（10）的锁相环。
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公开(公告)号：EP2843432A4
公开(公告)日：2016-04-27
申请号：EP12875297
申请日：2012-04-27
CPC分类号： G01R31/362 , B60L11/1862 , G01R31/3658 , G01R35/00 , H01M10/482 , H01M2220/20 , H02J7/0029 , H03M1/38
摘要： A battery monitoring device for monitoring a cell group made by connecting a plurality of single battery cells in series includes a first switching circuit configured to select, as a measurement target voltage, any one of a plurality of types of voltages including the cell voltages of the single battery cells in the cell group, a differential amplifier circuit including a first input terminal and a second input terminal, and configured to convert the measurement target voltage, which is selected by the first switching circuit and input to between the first input terminal and the second input terminal, into a voltage in a predetermined range by performing differential amplification, and an AD converter configured to measure the measurement target voltage which is selected by the first switching circuit and converted by the differential amplifier circuit, and output a digital signal according to the measurement result, wherein an abnormality detection voltage, with which abnormality in a differential amplification characteristic of the differential amplifier circuit is detected, is output to the AD converter.
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公开(公告)号：EP2940862A1
公开(公告)日：2015-11-04
申请号：EP15163434.2
申请日：2015-04-13
申请人： Analog Devices, Inc.
发明人： DINC, Huseyin , ALI, Ahmed M. A.
IPC分类号： H03F3/50 , H03K19/0185
摘要： Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an analog signal into its digital representation by comparing analog input signals against one or more voltage references provided by those circuits. In many applications, the speed and accuracy of such voltage references are very important. The speed of the voltage references is related to the physical properties of the devices in the circuit. The accuracy of the voltage reference is directly related to the circuit's ability to trim the full-scale voltage output. The present disclosure describes a fast and efficient reference buffer with a wide trim range which is particular suitable for submicron processes and high speed applications. The reference buffer comprises a plurality of diode-connected transistors, which can be selected to turn on or off using a controller to provide a wide trim range.
摘要翻译： 用于产生电压基准的电路在电子设备中很常见。 例如，这些电路用于模拟 - 数字转换器，通过将模拟输入信号与由这些电路提供的一个或多个电压参考值进行比较，将模拟信号转换为数字表示。 在许多应用中，这种电压参考的速度和精度是非常重要的。 电压基准的速度与电路中器件的物理特性有关。 电压参考的精度与电路修整满量程电压输出的能力直接相关。 本公开描述了具有宽的修整范围的快速和有效的参考缓冲器，其特别适用于亚微米工艺和高速应用。 参考缓冲器包括多个二极管连接的晶体管，其可以选择使用控制器导通或关断以提供宽的修整范围。
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公开(公告)号：EP2849346A1
公开(公告)日：2015-03-18
申请号：EP13184044.9
申请日：2013-09-12
CPC分类号： H03M1/002 , H03M1/1215 , H03M1/125 , H03M1/38 , H03M1/462
摘要： Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.
摘要翻译： 混合信号电路，包括：被配置为以时间交织的方式操作的ADC单元的阵列，并且每个可在一系列时间窗口中的每一个操作以将模拟输入值转换成相应的数字输出值，每个转换包括 子转换操作的顺序，通过完成先前的子转换操作触发序列的每个连续的子转换操作; 以及控制器，其中：所述ADC单元中的至少一个可操作以用作报告ADC单元，并针对一个或多个所监视的所述转换中的每一个指示在所述转换期间完成的所述子转换操作中的特定一个 时间窗; 并且所述控制器可操作以考虑至少一个这样的指示并且根据所述或每个所考虑的指示来控制所述电路。
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