公开(公告)号：EP3699795A1

公开(公告)日：2020-08-26

申请号：EP20155110.8

申请日：2020-02-03

申请人： INTEL Corporation

发明人： Gabor, Ron ,  Alameldeen, Alaa ,  Basak, Abhishek ,  Liu, Fangfei ,  McKeen, Francis ,  Nuzman, Joseph ,  Rozas, Carlos ,  Yanover, Igor ,  Zou, Xiang

IPC分类号： G06F21/52 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/1027 ,  G06F21/75

摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：EP3411791A1

公开(公告)日：2018-12-12

申请号：EP17703590.4

申请日：2017-01-25

申请人： Microsoft Technology Licensing, LLC

发明人： FOLTZ, Forrest Curtis

IPC分类号： G06F9/50 ,  G06F12/0806

CPC分类号： G06F17/30132 ,  G06F3/0613 ,  G06F3/0643 ,  G06F3/067 ,  G06F9/5016 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0868 ,  G06F12/0877 ,  G06F12/0888 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/283 ,  G06F2212/502

摘要： In various embodiments, methods and systems, for implementing modular data operations, are provided. A data access request, associated with data, is received at a data access component. The data access component selectively implements modular data operations functionality based on configuration settings. A translation table associated with a working set is accessed, based on the configuration settings of the data access component, to determine a location for executing the data access request. The data access request is executed using the cache store or a backing store associated with the working set. The data access request is executed using the location that is determined using the translation table of the working set. The data access request is executed using the cache store when the data is cached in the cache store and the data access requested is executed based on the backing store when the data is un-cached in the cache store.

公开(公告)号：EP3185148A4

公开(公告)日：2017-11-29

申请号：EP16732876

申请日：2016-01-04

申请人： HUAWEI TECH CO LTD

发明人： XIAO YULEI ,  YE TAO

IPC分类号： G06F17/30 ,  G06F3/06 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0868

CPC分类号： G06F17/30371 ,  G06F3/06 ,  G06F11/2043 ,  G06F12/0806 ,  G06F12/0868 ,  G06F17/30368 ,  G06F17/30575

摘要： A resource coordination method, an apparatus, and a system for a database cluster are provided. The method includes: An active coordinator node obtains status information corresponding to each processing node in multiple processing nodes (201), where the status information is used to indicate an operating load status of the processing node; determines, according to the status information corresponding to each processing node in multiple processing nodes, whether the active coordinator node has an idle resource whose capacity is a preset threshold X (203); and if the active coordinator node has the idle resource whose capacity is the preset threshold X, instructs each processing node to upload subsequently generated clean page data to the active coordinator node (205). More data generated by a processing node can be stored in a coordinator node by using this method. An idle resource on the coordinator node and a high-speed communication feature of a communication interface between the coordinator node and the processing node are fully used, so that starting of the processing node is more rapid and efficient.

公开(公告)号：EP4137954A1

公开(公告)日：2023-02-22

申请号：EP22188131.1

申请日：2022-08-01

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： DVORAK, Vaclav ,  RENNIG, Fred

IPC分类号： G06F13/42 ,  G06F12/0806 ,  G06F13/40 ,  H04L12/40 ,  G06F13/28 ,  G06F13/38

摘要： A processing system (10a) is described. The processing system comprises a Serial Peripheral Interface, SPI, communication interface (50), a microprocessor (1020), a memory controller (100) connected to a memory (104, 104b), and two DMA channels (DMA 1 , DMA 2 ) configured to transfer packets between the SPI interface (50) and the memory (104b). In particular, the processing system comprises an edge detector (600, 620) configured to assert a first control signal (IRQ 60 ) in response to a falling edge in the reception signal (RXD), a first hardware timer circuit (60) configure to, when enabled, generate a clock signal (PWM) for the SPI communication interface (50) and a second hardware timer circuit (62) configure to, when enabled, increase a count value and assert a second control signal (IRQ 62 ) in response to determining that the count value reaches a given threshold value.
Specifically, the processing system (10a) is configured to manage a CAN FD Light data transmission mode and/or CAN FD Light data reception mode by using the SPI communication interface. For example, in the CAN FD Light data reception mode, the microprocessor (1020) activates a slave mode of the SPI communication interface (50), enables the first hardware timer circuit (60) and the second hardware timer circuit (62) in response to the first control signal (IRQ 60 ), whereby the second DMA channel (DMA 2 ) transfers packets from the SPI communication interface (50) to the memory (104b), thereby sequentially transferring a reception CAN FD Light frame from the SPI communication interface (50) to the memory (104b), and reads the reception CAN FD Light frame from the memory (104b) in response to the second control signal (IRQ 62 ).

公开(公告)号：EP3598309B1

公开(公告)日：2022-05-11

申请号：EP19190794.8

申请日：2015-07-07

发明人： WOOLLEY, Brandon

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F9/46 ,  G06F9/455 ,  G06F9/54 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/0806 ,  G06F12/1081 ,  G06F9/4401

公开(公告)号：EP3111333B1

公开(公告)日：2022-03-30

申请号：EP14884199.2

申请日：2014-02-27

发明人： SOLIHIN, Yan

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F13/14 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0813 ,  G06F11/34

公开(公告)号：EP3866020A1

公开(公告)日：2021-08-18

申请号：EP21165826.5

申请日：2020-09-15

申请人： INTEL Corporation

发明人： Blankenship, Robert G. ,  Choudhary, Swadesh ,  Abraham, Vinit Mathew ,  Liu, Yen-Cheng ,  Kumar, Sailesh ,  Gadey, Siva Prasad

IPC分类号： G06F13/42 ,  G06F12/0806

摘要： This disclosure pertains to point-to-point interconnects. In particular, an apparatus comprising an agent block comprising circuitry to support a plurality of coherent protocols, is provided. The agent block comprises an interface to communicate with a fabric. The interface comprises: a global channel to use a first set of wires, wherein the global channel is to carry signals for initialization of the interface; a request channel to use a second set of wires, wherein the request channel is to carry address and protocol level command information associated with requests sent from the agent block; a response channel to use a third set of wires, wherein the response channel is to carry responses to the requests sent from the agent block; and a data channel to use a fourth set of wires, wherein the data channel is to carry data transfers from the agent block to other agents via the fabric.

公开(公告)号：EP3598309A1

公开(公告)日：2020-01-22

申请号：EP19190794.8

申请日：2015-07-07

申请人： Raytheon Company

发明人： WOOLLEY, Brandon

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F9/46 ,  G06F9/455 ,  G06F9/54 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/0806 ,  G06F12/1081 ,  G06F9/4401

摘要： A separation kernel isolating memory domains within a shared system memory (103, 301, 401) is executed on the cores (202) of a multicore processor (101, 201a-201h) having hardware security enforcement for static virtual address mappings, to implement an efficient embedded multi-level security system (100). Shared caches (208, 209) are disabled to isolate domains accessible to select cores and reduce security risks from data co-mingling.

公开(公告)号：EP3547135A1

公开(公告)日：2019-10-02

申请号：EP19169817.4

申请日：2016-11-30

申请人： Intel Corporation

发明人： Chaffin, Benjamin C. ,  Kyanko, Robert J. ,  Sodani, Avinash

IPC分类号： G06F9/52 ,  G06F12/0806

摘要： Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. For example, a processor comprises: a data cache; an instruction cache; instruction fetch circuitry to fetch the MONITOR instruction and the MWAIT instruction from the instruction cache; instruction decode circuitry to decode the fetched MONITOR instruction and MWAIT instruction; a model specific register (MSR) to be configured in a user-monitor-wait-enabled execution state to enable the MONITOR instruction and the MWAIT instruction to be executed at a privilege level; and execution circuitry to execute the MONITOR instruction and the MWAIT instruction. When the MSR is not configured in the user monitor-wait-enabled execution state, execution of the MONITOR instruction and the MWAIT instruction is restricted to the privilege level zero. The MONITOR instruction is to specify a linear address range to be monitored, the linear address range to have a write-back memory type for caching in the data cache. The MWAIT instruction is to specify an implementation-dependent-optimized state for power management and to indicate to the processor to enter the implementation-dependent-optimized state for power management. The execution circuitry is configured to detect a store operation to the linear address range, and if the implementation-dependent-optimized state for power management is entered in response to execution of the monitor-wait instruction, the implementation-dependent-optimized state for power management is maintained until the store operation to the linear address range is detected.

公开(公告)号：EP3519974A1

公开(公告)日：2019-08-07

申请号：EP17857349.9

申请日：2017-09-27

申请人： Level 3 Communications, LLC

发明人： POWER, William R. ,  JAKOBOWSKI, Pawel

IPC分类号： G06F12/0888 ,  G06F12/0802 ,  G06F12/0806