公开(公告)号：EP3226231A4

公开(公告)日：2018-06-13

申请号：EP15777598

申请日：2015-03-13

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： MA ZHANJIE

IPC分类号： G09G3/3266 ,  G09G3/3208 ,  G11C19/28

CPC分类号： G09G3/3291 ,  G09G3/3225 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28 ,  H03K5/00 ,  H03K5/135 ,  H03K5/1506

摘要： An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).

公开(公告)号：EP2509077B1

公开(公告)日：2018-05-09

申请号：EP12162618.8

申请日：2012-03-30

申请人： Beijing BOE Optoelectronics Technology Co., Ltd.

发明人： Chen, Xi ,  Cui, Wenhai

IPC分类号： G11C19/28 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3674 ,  G09G2310/0286

摘要： The present invention discloses a shifting register and an apparatus for driving gate lines, and it relates to Liquid Crystal Display technical field, for reducing the noise of a shifting register during non-working period. The shifting register comprises: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a capacitor and a pull-down module, and the pull-down module is connected among a clock signal port, a first node and a signal output terminal, and further is connected to a low level signal terminal, for maintaining the first node and the signal output terminal to be at low level during the non-working period of the shifting register. The apparatus for driving gate lines comprises a plurality of above shifting registers connected in serial. The present invention is applicable to driving gate lines.

公开(公告)号：EP2963635B1

公开(公告)日：2018-04-11

申请号：EP13866489.1

申请日：2013-05-21

申请人： BOE Technology Group Co., Ltd. ,  Hefei BOE Optoelectronics Technology Co., Ltd.

发明人： ZENG, Mian ,  LI, Xiaohe ,  KIM, Jaikwang

IPC分类号： G09G3/20 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3648 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/043

摘要： Provided is a shift register unit, a gate driving apparatus and a display device capable of increasing a lifespan of a shift register. The shift register unit according to the present disclosure includes: a first thin film field effect transistor, a drain thereof connected with a first signal terminal, a source thereof connected with the outputting node at the present stage, a gate thereof connected with a first node; a second thin film field effect transistor, a drain thereof connected with the first signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the first node; a third thin film field effect transistor, a drain thereof connected with a second signal terminal, a source thereof connected with the outputting node at the present stage, and a gate thereof connected with a second node; a fourth thin film field effect transistor, a drain thereof connected with the second signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the second node; and a node voltage control module, configured to control the first node and the second node to be in a high potential state alternatively when the shift register unit is in a pulling-down phase. The present disclosure increases the lifespan of the shift register.

公开(公告)号：EP2874140B1

公开(公告)日：2018-04-04

申请号：EP12880722.9

申请日：2012-11-21

申请人： BOE Technology Group Co., Ltd.

发明人： KIM, Tae Gyu ,  KIM, Pil Seok ,  WANG, Ying

IPC分类号： G09G3/3266 ,  G11C19/28

CPC分类号： H05B33/0896 ,  G09G3/3266 ,  G09G2300/0861 ,  G09G2310/0286 ,  G11C19/184

摘要： A light-emitting control circuit, a light-emitting control method and a shift register. The light-emitting control circuit comprises an inputting terminal (Input), an input sampling unit (11), an outputting unit (12), a resetting unit (13), an output pulling-down unit (14) and an outputting terminal for a light-emitting control signal (EM[n]). The input sampling unit (11) samples an input signal under a control of a first clock signal (CK1); the outputting unit (12) generates a light-emitting control signal under a control of a second clock signal (CK2) after the input sampling unit (11) samples the input signal; the resetting unit (13) resets the light-emitting control signal through the output pulling-down unit (14) under a control of a third clock signal (13). An OLED device is in an OFF state during a process for writing display data into pixel cells and the OLED device is turned on to emit light after the display data is written into the pixel cells, thus a display image is guaranteed not to generate flickers due to an unstable state of a pixel circuit as the data is written.

公开(公告)号：EP2851744B1

公开(公告)日：2018-01-03

申请号：EP13790794.5

申请日：2013-05-09

申请人： Sharp Kabushiki Kaisha

发明人： MORI Takahiro

IPC分类号： G02F1/1345 ,  G02F1/1339 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28

CPC分类号： G02F1/1339 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/1345 ,  G02F1/136213 ,  G02F1/1368 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/28 ,  G11C19/287

摘要： The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

公开(公告)号：EP3188191A4

公开(公告)日：2017-11-01

申请号：EP14903436

申请日：2014-09-30

申请人： HUAWEI TECH CO LTD

发明人： HE RUI ,  XU RONGGANG ,  ZHAO JUNFENG

IPC分类号： G11C19/28 ,  G11C13/00 ,  G11C14/00 ,  H03K3/00

CPC分类号： G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/009 ,  G11C19/28 ,  G11C19/287 ,  G11C2013/0073 ,  H03K3/356104 ,  H03K3/356113 ,  H03K3/356121

摘要： A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches, where a first switch is closed when a first end of the first switch is at a low level, a fourth switch is closed when a first end of the fourth switch is at a low level, a second switch is closed when a first end of the second switch is at a high level, and a third switch is closed when a first end of the third switch is at a high level; a second end of the first switch and a second end of the third switch are connected to a negative input end of the resistive random-access memory; a second end of the second switch and a second end of the fourth switch are connected to a positive input end of the resistive random-access memory; the first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are connected to an output end of a previous-stage circuit for implementing a shift operation; a third end of the first switch and a third end of the second switch are connected to a bias voltage end; and a third end of the third switch and a third end of the fourth switch are connected to a ground end. The shift circuit has a simple structure and can improve computational efficiency.

公开(公告)号：EP3217387A1

公开(公告)日：2017-09-13

申请号：EP15762458.6

申请日：2015-03-19

申请人： BOE Technology Group Co., Ltd.

发明人： ZHANG, Yuanbo ,  HAN, Seungwoo ,  IM, Yunsik

IPC分类号： G09G3/36 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2330/06 ,  G11C19/28

摘要： The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module, wherein the input module is connected to a signal input end and a pull-up control node; the pull-up module is connected to the pull-up control node, a first clock signal port and a signal output end; the pull-down control module is connected to a pull-down control node and a second clock signal port; the pull-down module is connected to the pull-down control node, the pull-up control node and a low level signal; the discharge module comprises a discharge capacitor, a first end of the discharge capacitor being connected to the pull-up module and the pull-up control node, a second end being connected to an output signal reset input end; the reset module is connected to a reset signal input end, the pull-up control node and the low level signal.

摘要翻译： 本发明提供一种移位寄存器单元，栅极驱动电路和显示装置，属于显示技术领域。 本发明的移位寄存器单元包括：输入模块，上拉模块，下拉控制模块，下拉模块，复位模块和放电模块，其中输入模块连接到信号 输入端和上拉控制节点; 所述上拉模块连接至所述上拉控制节点，第一时钟信号端口和信号输出端; 所述下拉控制模块连接至下拉控制节点和第二时钟信号端口; 所述下拉模块连接至所述下拉控制节点，所述上拉控制节点和低电平信号; 所述放电模块包括放电电容，所述放电电容的第一端连接上拉模块和上拉控制节点，第二端连接输出信号复位输入端; 复位模块连接复位信号输入端，上拉控制节点和低电平信号。

公开(公告)号：EP3091532A4

公开(公告)日：2017-08-30

申请号：EP14876723

申请日：2014-12-29

申请人： KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CT CO LTD ,  KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO LTD

发明人： YANG NAN ,  HU SIMING ,  ZHANG TINGTING ,  ZHANG XIAOBAO ,  NAGAI HAJIME ,  HUANG XIUQI

IPC分类号： G09G3/3266 ,  G11C19/28

CPC分类号： G09G3/3266 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A scanning drive circuit and an organic light-emitting display. The scanning drive circuit comprises a first scanning driver which outputs selection signals in sequence, and a second scanning driver which outputs transmitting signals in sequence. The first scanning driver comprises a plurality of first cascade structures, and the second scanning driver comprises a plurality of second cascade structures. Each cascade structure of the first cascade structures or/and the second cascade structures comprises nine transistors and one capacitor. The scanning drive circuit adopts fewer clock signals and transistors, so that the reliability of the product circuit can be significantly improved, and at the same time design costs and production costs of products are reduced as well.

摘要翻译： 扫描驱动电路和有机发光显示器。 扫描驱动电路包括依次输出选择信号的第一扫描驱动器和顺序输出发送信号的第二扫描驱动器。 第一扫描驱动器包括多个第一级联结构，并且第二扫描驱动器包括多个第二级联结构。 第一级联结构或/和第二级联结构的每个级联结构包括九个晶体管和一个电容器。 扫描驱动电路采用较少的时钟信号和晶体管，从而显着提高了产品电路的可靠性，同时也降低了产品的设计成本和生产成本。

公开(公告)号：EP3086312A4

公开(公告)日：2017-07-26

申请号：EP14861172

申请日：2014-04-02

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： CAO KUN

IPC分类号： G09G3/36 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： There are provided a shift register unit, a gate driving circuit and a display device, which enable gate lines in non-output rows to remain in the state of no signal outputting. The shift register unit comprises an input module (10), a pull-up module (20), a pull-down control module (30), a first pull-down module (31), a second pull-down module (40) and a reset module (50). In the non-output time, the first pull-down module and the second pull-down module pull down the output voltages of the pull-up modules connected thereto to a low level alternately, thereby enabling gate lines in non-output rows to remain in the state of no signal outputting.

摘要翻译： 提供了一种移位寄存器单元，栅极驱动电路和显示装置，其使非输出行中的栅极线保持处于无信号输出状态。 移位寄存器单元包括输入模块（10），上拉模块（20），下拉控制模块（30），第一下拉模块（31），第二下拉模块（40） 和重置模块（50）。 在非输出时间中，第一下拉模块和第二下拉模块交替地将与其连接的上拉模块的输出电压下拉到低电平，从而使得非输出行中的栅极线保留 在没有信号输出的状态下。

公开(公告)号：EP3174038A1

公开(公告)日：2017-05-31

申请号：EP16199284.7

申请日：2016-11-17

申请人： LG Display Co., Ltd.

发明人： KIM, Byungil

IPC分类号： G09G3/20 ,  G11C19/14 ,  G11C19/28

CPC分类号： G09G3/3266 ,  G02F1/133308 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/3275 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  G11C19/287 ,  H01L27/3276

摘要： Provided are a gate driving circuit and a display device using the same, and the gate driving circuit includes a shift register which includes stages. The n-th stage (n is a positive integer) includes an auto reset circuit (31) that receives a first clock (CLKA) and a carry signal (Gout_Pre) received from an (n-1)-th stage, regulates a Q node (Q) to be at a low voltage when the first clock (CLKA) is at a high voltage and the carry signal (Gout_Pre) is at a low voltage, and regulates the Q node (Q) to be at a high voltage when both of the first clock (CLKA) and the carry signal (Gout_Pre) are at a high voltage.

摘要翻译： 提供了一种栅极驱动电路和使用该栅极驱动电路的显示装置，并且该栅极驱动电路包括包括多个级的移位寄存器。 第n级（n是正整数）包括接收从第（n-1）级接收的第一时钟（CLKA）和进位信号（Gout_Pre）的自动复位电路（31），调节Q 当第一时钟（CLKA）处于高电压且进位信号（Gout_Pre）处于低电压时，节点（Q）处于低电压，并且当节点（Q）处于高电压时将Q节点 第一时钟（CLKA）和进位信号（Gout_Pre）都处于高电压。