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公开(公告)号:EP3940778A1
公开(公告)日:2022-01-19
申请号:EP21185217.3
申请日:2021-07-13
发明人: CHIA, Han-Jong , LIN, Meng-Han , LIN, Yu-Ming
IPC分类号: H01L27/11597 , H01L27/11587 , H01L27/1159 , H01L29/66 , H01L29/78 , H01L27/11578
摘要: A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are connected to source and drain pillars penetrating through the word line. The memory cell further contains a channel layer and a charge storage dielectric layer, the charge storage dielectric layer may be a ferroelectric layer. A method for fabricating a memory device is also provided.
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公开(公告)号:EP3921865A1
公开(公告)日:2021-12-15
申请号:EP20915413.7
申请日:2020-01-21
发明人: ZHANG, Kun , SONG, Haojie , BAO, Kun , XIA, Zhiliang
IPC分类号: H01L23/535 , H01L23/48 , H01L27/11563 , H01L27/11578
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公开(公告)号:EP3915148A1
公开(公告)日:2021-12-01
申请号:EP19953130.2
申请日:2019-11-22
发明人: LIU, Liheng , YANG, Chuan , PENG, Shuangshuang
IPC分类号: H01L27/11578 , H01L27/11568 , H01L27/11563
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44.
公开(公告)号:EP3910672A1
公开(公告)日:2021-11-17
申请号:EP21182943.7
申请日:2018-11-16
发明人: NISHIDA, Akio
IPC分类号: H01L27/11551 , H01L27/11524 , H01L27/11578 , H01L27/1157 , H01L27/11529 , H01L21/8238
摘要: A first die includes a three-dimensional memory device and first copper pads. A second die includes a peripheral logic circuitry containing CMOS devices located on the semiconductor substrate and second copper pads. A bonded assembly is formed by bonding the first copper pads with the second copper pads through copper interdiffusion to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die.
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45.
公开(公告)号:EP3867953A1
公开(公告)日:2021-08-25
申请号:EP19899779.3
申请日:2019-04-09
发明人: XIAO, Lihong
IPC分类号: H01L27/11578
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公开(公告)号:EP3580782A1
公开(公告)日:2019-12-18
申请号:EP18849168.2
申请日:2018-03-01
发明人: LU, Zhenyu , CHEN, Jun , ZHU, Jifeng , HU, Yushi , TAO, Qian , YANG, Simon Shi-Ning , YANG, Steve Weiyi
IPC分类号: H01L27/11578 , H01L27/11524
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47.
公开(公告)号:EP3440700A1
公开(公告)日:2019-02-13
申请号:EP17776028.7
申请日:2017-01-11
申请人: Intel Corporation
发明人: THIMMEGOWDA, Deepak , YIP, Aaron , HELM, Mark , LI, Yongna
IPC分类号: H01L27/11578 , H01L27/11575 , H01L27/1157 , H01L27/11551 , H01L27/11548 , H01L27/11524 , H01L27/11597 , H01L27/11595 , H01L27/24
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公开(公告)号:EP3375012A1
公开(公告)日:2018-09-19
申请号:EP16823449.0
申请日:2016-12-19
发明人: OGAWA, Hiroyuki , TOYAMA, Fumiaki , ARIKI, Takuya
IPC分类号: H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11565 , H01L27/11575 , H01L27/11578
摘要: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
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公开(公告)号:EP4176466A1
公开(公告)日:2023-05-10
申请号:EP21836885.0
申请日:2021-06-30
申请人: Invensas Corporation
IPC分类号: H01L27/11578 , H01L27/11565 , H01L27/11568 , H01L27/11551 , H01L27/11519 , H01L27/11521
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50.
公开(公告)号:EP4136676A1
公开(公告)日:2023-02-22
申请号:EP21788337.0
申请日:2021-02-24
发明人: HOSSAIN, S M Istiaque , LARSEN, Christopher J. , CHANDOLU, Anilkumar , MCKINSEY, Wesley O. , JOHN, Tom J. , DHAYALAN, Arun Kumar , MOKHNA RAU, Prakash Rau
IPC分类号: H01L27/11578 , H01L27/11575 , H01L27/11568 , H01L21/8234 , G06F3/06
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