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    FIELD EFFECT TRANSISTOR WITH ELEVATED ACTIVE REGIONS AND METHODS OF MANUFACTURING THE SAME
    2.
    发明公开
    FIELD EFFECT TRANSISTOR WITH ELEVATED ACTIVE REGIONS AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：EP3916801A1

    公开(公告)日：2021-12-01

    申请号：EP21182810.8

    申请日：2016-04-20

    申请人： SanDisk Technologies LLC

    发明人： NISHIKAWA, Masatoshi ,  INOUE, Akira ,  TOYAMA, Fumiaki

    IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11556

    摘要： A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer (60) over gate stacks (50; 52; 58), forming via cavities (169) laterally spaced from the gate stacks (50; 52; 58), selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions (136S; 136D). Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities (169) can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region (136S) and a drain region (136D). Optionally, embedded active regions (232S; 232D) for additional devices can be formed prior to formation of the contiguous dielectric material layer (60). Raised active regions (236S; 236D) contacting a top surface of a substrate (10) can be formed simultaneously with formation of the elevated active regions (136S; 136D) that are vertically spaced from the top surface.

    WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY
    4.
    发明公开
    WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：EP3375012A1

    公开(公告)日：2018-09-19

    申请号：EP16823449.0

    申请日：2016-12-19

    申请人： SanDisk Technologies LLC

    发明人： OGAWA, Hiroyuki ,  TOYAMA, Fumiaki ,  ARIKI, Takuya

    IPC分类号： H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578

    摘要： The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

    FIELD EFFECT TRANSISTOR WITH A MULTILEVEL GATE ELECTRODE FOR INTEGRATION WITH A MULTILEVEL MEMORY DEVICE
    5.
    发明公开
    FIELD EFFECT TRANSISTOR WITH A MULTILEVEL GATE ELECTRODE FOR INTEGRATION WITH A MULTILEVEL MEMORY DEVICE 审中-公开

    公开(公告)号：EP3326205A1

    公开(公告)日：2018-05-30

    申请号：EP16760882.7

    申请日：2016-08-26

    申请人： SanDisk Technologies LLC

    发明人： NISHIKAWA, Masatoshi ,  KOKETSU, Hiroaki ,  TOYAMA, Fumiaki ,  OH, Junji

    IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L27/115

    摘要： A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.