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286 条记录 (耗时 0.015 秒)

    TTL Buffer circuit
    42.
    发明公开
    TTL Buffer circuit 失效
    TTL-Pufferschaltung。

    公开(公告)号：EP0250007A2

    公开(公告)日：1987-12-23

    申请号：EP87200416.3

    申请日：1987-03-06

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Tavana, Danash M. ,  Wong, Sing Y.

    IPC分类号： H03K19/088 ,  H03K19/013

    CPC分类号： H03K19/0136 ,  H03K19/088

    摘要： A TTL buffer circuit (30) which is switched by an increasing or decreasing voltage input signal (Ii) at the same threshold, and which switches at increased speed. A bleed transistor (Q6) allows the phase splitter transistor base to begin charging before the bleed transistor (Q6) turns on. While the phase splitter transistor (Q3) is on, the bleed transistor current is limited to avoid interfering with operation of the phase splitter transistor (Q3). When the phase splitter control lead current is cut off, the phase splitter base capacitance is discharged rapidly through the bleed transistor (Q6), at the end of which the phase splitter and bleed transistors (Q3, Q6) stop conducting.

    摘要翻译： TTL缓冲电路（30），其以相同阈值的增加或减少的电压输入信号（Ii）切换，并以增加的速度切换。 放电晶体管（Q6）允许分相晶体管基极在放电晶体管（Q6）导通之前开始充电。 当分相晶体管（Q3）导通时，放电晶体管电流受到限制，以避免干扰分相晶体管（Q3）的工作。 当分相器控制引线电流被切断时，相分离器基极电容通过放电晶体管（Q6）快速放电，其中分相器和放电晶体管（Q3，Q6）停止导通。

    Logic circuit
    43.
    发明公开
    Logic circuit 失效
    逻辑电路

    公开(公告)号：EP0219867A3

    公开(公告)日：1987-12-23

    申请号：EP86114694

    申请日：1986-10-23

    申请人： NEC CORPORATION

    发明人： Dasai, Teiji ,  Hiki, Yoshimasa

    IPC分类号： H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K19/0136

    摘要： A current-mode logic circuit includes a pair of input bipolar transistors (16, 36) coupled in the emitter-coupled single differential circuit configuration, one (16) of which input transistors is connected at its base to receive an input signal and the other input transistor (36) is connected at its base to receive a reference voltage. The collector of each of the input transistor is connected to a base of an emitter-follower driver (42, 44) which is in turn connected at its collector to a voltage supply terminal (20) and at its emitter through load means to another voltage supply terminal (50). The emitters of these output transistors are connected to a pair of output terminals (52, 54) to generate a pair of complementary logic signals. Further, there are provided first and second auxiliary transistors (60, 12) connected in the cross-coupled flip-flop configuration and connected at their collectors to the emitters of the first and second output bipolar transistors (42, 44), respectively.

    摘要翻译： 电流模式逻辑电路包括以发射极耦合单差分电路配置耦合的一对输入双极晶体管（16,36），其中一个（16）的输入晶体管在其基极连接以接收输入信号，而另一个 输入晶体管（36）在其基极连接以接收参考电压。 每个输入晶体管的集电极连接到发射极跟随器驱动器（42,44）的基极，该发射极跟随器驱动器依次在其集电极连接到电压供应端子（20）并且在其发射极通过负载装置连接到另一个电压 供电端子（50）。 这些输出晶体管的发射极连接到一对输出端子（52,54）以产生一对互补的逻辑信号。 此外，提供了以交叉耦合的触发器配置连接的第一和第二辅助晶体管（60,12），并且它们的集电极分别连接到第一和第二输出双极晶体管（42,44）的发射极。

    An emitter coupled logic circuit
    44.
    发明公开
    An emitter coupled logic circuit 失效
    Emittergekoppelte logische Schaltung。

    公开(公告)号：EP0224216A2

    公开(公告)日：1987-06-03

    申请号：EP86116182.6

    申请日：1986-11-21

    申请人： NEC CORPORATION

    发明人： Umeki, Yoshitaka c/o NEC Corporation

    IPC分类号： H03K19/086 ,  H03K19/013

    CPC分类号： H03K19/086 ,  H03K19/0136

    摘要： The ECL circuit includes a plurality of input terminals (1, 2, 3), a current source (8), a reference transistor (12) having an emitter connected to the current source, a base (7) receiving a reference voltage and a collector connected to a first resistor (15), a plurality of input transistors (9, 10, 11) each having an emitter connected to the current source (8), a collector connected to a second resistor (14) and a base connected to one of the input terminals (1, 2, 3), a plurality of pull-down resistors (57, 58, 59) each connected between the base and the emitter of one of the input transistors, an emitter follower transistor (13) having a base connected to the collector of the reference transistor (12) or a common connection point of collectors of the input transistors and an emitter connected to an output terminal (4) and a third resistor (16).

    摘要翻译： ECL电路包括多个输入端子（1,2,3），电流源（8），具有连接到电流源的发射极的参考晶体管（12），接收参考电压的基极（7）和 集电极，连接到第一电阻器（15），多个输入晶体管（9,10,11），每个输入晶体管具有连接到电流源（8）的发射极，连接到第二电阻器（14）的集电极和连接到 输入端子（1,2,3）中的一个，多个下拉电阻器（57,58,59），每个连接在一个输入晶体管的基极和发射极之间，射极跟随器晶体管（13）具有 连接到参考晶体管（12）的集电极的基极或输入晶体管的集电极的公共连接点和连接到输出端子（4）和第三电阻器（16）的发射极。

    EMITTER COLLECTOR COUPLED LOGIC.
    46.
    发明公开
    EMITTER COLLECTOR COUPLED LOGIC. 失效
    AM AUSSTRAHLERKOLLEKTOR耦合的逻辑电路。

    公开(公告)号：EP0155305A4

    公开(公告)日：1986-12-08

    申请号：EP84903465

    申请日：1984-09-06

    申请人： ADVANCED MICRO DEVICES INC

    发明人： VARADARAJAN HEMMIGE D

    IPC分类号： H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K17/16

    CPC分类号： H03K19/086 ,  H03K19/013

    摘要： The reference portion of a primitive current switch (QA, QB, and QR) used in emitter coupled logic or current mode logic is modified by introducing a slow device (QRR) as the reference element in order to enhance the speed of turn on and turn off of the input elements (QA and QB). In particular, the reference transistor (QR) of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode (QRR) in order to bypass the emitter dynamic resistance. The emitter time constant of the reference QR is thereby increased so that the voltage on the common source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor QA is switched on or off significantly faster.

    Emitter coupled logic circuit
    48.
    发明公开
    Emitter coupled logic circuit 失效
    Emittergekoppelte Logikschaltung。

    公开(公告)号：EP0176799A1

    公开(公告)日：1986-04-09

    申请号：EP85111239.1

    申请日：1985-09-05

    申请人： FUJITSU LIMITED

    发明人： Kanai, Yasunori ,  Saitoh, Taichi

    IPC分类号： H03K19/086 ,  H03K19/013

    CPC分类号： H03K19/0136 ,  H03K19/001 ,  H03K19/086

    摘要： ECL (Emitter Coupled Logic) circuit is improved to increase its ability to drive a large capacity load (CL) to drive a large fan-out circuit, and the power consumption per gate is reduced. The output circuit (OB1) of the ECL circuit is provided with an emitter follower transistor (T6) of which current is detected by a detecting transistor (T7). A current control transistor (T8) is provided to charge up quickly the load capacitance (CL) under the control of the detecting transistor (T7). So the voltage build down of the output signal is especially improved. One of the emitter follower transistor (T6) and the current transistor (T8) is always cut off when the other is in a conductive state. So the current running through the circuit is reduced.

    摘要翻译： ECL（发射极耦合逻辑）电路得到改进，以提高其驱动大容量负载（CL）来驱动大型扇出电路的能力，并降低每个门的功耗。 ECL电路的输出电路（OB1）设有由检测晶体管（T7）检测电流的射极跟随器晶体管（T6）。 提供电流控制晶体管（T8）以在检测晶体管（T7）的控制下快速充电负载电容（CL）。 因此，输出信号的电压降低特别提高。 当另一个处于导通状态时，射极跟随器晶体管（T6）和电流晶体管（T8）中的一个总是截止。 所以通过电路的电流减少了。

    Transistor-transistor logic circuits
    50.
    发明公开
    Transistor-transistor logic circuits 失效
    晶体管逻辑电路

    公开(公告)号：EP0068832A3

    公开(公告)日：1984-05-23

    申请号：EP82303309

    申请日：1982-06-24

    申请人： FUJITSU LIMITED

    发明人： Ohba, Osam

    IPC分类号： H03K19/013 ,  H03K19/088 ,  H01L27/08

    CPC分类号： H03K19/088

    摘要： A TTL fundamental logic circuit comprises an npn-type input transistor (Q1), an npn-type output transistor (02), and a pnp-type output transistor (Q3) whose emitter is connected to the collector of the npn-type output transistor, whose base is connected to the base of the npn-type output transistor and whose collector is grounded. The pnp-type output transistor (Q3) is turned on when the npn-type output transistor (Q2) is turned off, and thereby the potential of the high level output signal can be decreased and the propagation delay of the fundamental logic circuit reduced.