公开(公告)号：EP2332142B1

公开(公告)日：2013-07-10

申请号：EP09792136.5

申请日：2009-09-01

申请人： QUALCOMM Incorporated

发明人： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

CPC分类号： G11C11/1673

公开(公告)号：EP2137734B1

公开(公告)日：2011-11-23

申请号：EP08745261.1

申请日：2008-04-07

申请人： QUALCOMM Incorporated

发明人： JUNG, Seong-ook ,  SANI, Mehdi, Hamidi ,  KANG, Seung H. ,  YOON, Sei Seung

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

摘要： Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region (454) of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region (452) of the word line transistor.

公开(公告)号：EP2126922B1

公开(公告)日：2011-11-23

申请号：EP08731574.3

申请日：2008-03-06

申请人： QUALCOMM INCORPORATED

发明人： YOON, Sei Seung ,  KANG, Seung H. ,  SANI, Mehdi Hamidi

IPC分类号： G11C11/16

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT- MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations.

公开(公告)号：EP2380175A1

公开(公告)日：2011-10-26

申请号：EP09802075.3

申请日：2009-12-18

申请人： QUALCOMM Incorporated

发明人： JUNG, Seong-Ook ,  KIM, Jisu ,  SONG, Jee-Hwan ,  KANG, Seung H. ,  YOON, Sei Seung ,  SANI, Mehdi Hamidi

IPC分类号： G11C11/16 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C7/12 ,  G11C11/1673

摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

公开(公告)号：EP2374129A1

公开(公告)日：2011-10-12

申请号：EP09793651.2

申请日：2009-12-07

申请人： QUALCOMM Incorporated

发明人： PARK, Dongkyu ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  ABU-RAHMA, Mohamed Hassan Soliman ,  YOON, Sei Seung

IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C11/16

CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2207/065 ,  G11C2207/2281

摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.

公开(公告)号：EP2332142A1

公开(公告)日：2011-06-15

申请号：EP09792136.5

申请日：2009-09-01

申请人： QUALCOMM Incorporated

发明人： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

CPC分类号： G11C11/1673

摘要： In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

公开(公告)号：EP2130206A1

公开(公告)日：2009-12-09

申请号：EP08743709.1

申请日：2008-03-06

申请人： QUALCOMM Incorporated

发明人： YOON, Sei Seung ,  KANG, Seung H. ,  SANI, Mehdi Hamidi

IPC分类号： G11C7/06 ,  G11C11/16

CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C11/1673

摘要： Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations.