利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.014 秒)

    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER
    3.
    发明公开
    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER 有权
    WITH DIGITAL DELAY应税检测放大器

    公开(公告)号：EP2374129A1

    公开(公告)日：2011-10-12

    申请号：EP09793651.2

    申请日：2009-12-07

    申请人： QUALCOMM Incorporated

    发明人： PARK, Dongkyu ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  ABU-RAHMA, Mohamed Hassan Soliman ,  YOON, Sei Seung

    IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C11/16

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2207/065 ,  G11C2207/2281

    摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.

    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS
    4.
    发明公开
    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS 有权
    存储设备电阻式存储器应用

    公开(公告)号：EP2332142A1

    公开(公告)日：2011-06-15

    申请号：EP09792136.5

    申请日：2009-09-01

    申请人： QUALCOMM Incorporated

    发明人： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

    CPC分类号： G11C11/1673

    摘要： In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

    MRAM DEVICE WITH SHARED SOURCE LINE
    5.
    发明公开
    MRAM DEVICE WITH SHARED SOURCE LINE 有权
    具有共同使用的源LINE MRAM安排

    公开(公告)号：EP2245630A1

    公开(公告)日：2010-11-03

    申请号：EP08861010.0

    申请日：2008-12-19

    申请人： QUALCOMM Incorporated

    发明人： YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

    摘要： In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. The memory cell may be formed by spin transfer torque magnetoresistive memory cells having selection field effect transistors. The memory cell may also be formed as complementary cell pairs. Half-selected cells are supplied with or across them to prevent read disturb.

    ADDRESS MULTIPLEXING IN PSEUDO-DUAL PORT MEMORY
    10.
    发明公开
    ADDRESS MULTIPLEXING IN PSEUDO-DUAL PORT MEMORY 有权
    PSEUDO-ZWEIPORT-SPEICHER中的ADRESSENMULTIPLEXEN

    公开(公告)号：EP2263235A1

    公开(公告)日：2010-12-22

    申请号：EP09718990.6

    申请日：2009-02-27

    申请人： QUALCOMM Incorporated

    发明人： JUNG, Changho ,  ZHONG, Cheng

    IPC分类号： G11C7/22 ,  G11C8/16

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： A pseudo-dual port memory address multiplexing system includes a control circuit (103) operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit (105) monitors a read operation and generates a switching signal (WCLK) when the read operation is determined to be complete. A multiplexer (104) is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

    摘要翻译： 伪双端口存储器地址多路复用系统包括控制电路，其操作以识别在单个时钟周期期间要完成的读请求和写请求。 自动跟踪电路监视读取操作，并且当读取操作被确定为完成时产生切换信号。 复用器响应于切换信号，用于在适当的时间选择性地向存储器地址单元提供读取地址和写入地址。