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    SENSE AMPLIFIER RANDOM NOISE STRESS
    1.
    发明公开
    SENSE AMPLIFIER RANDOM NOISE STRESS 审中-公开

    公开(公告)号：EP3411879A1

    公开(公告)日：2018-12-12

    申请号：EP17701773.8

    申请日：2017-01-09

    申请人： Qualcomm Incorporated

    发明人： JUNG, Chulmin ,  AHMED, Fahad ,  YOON, Sei Seung ,  KIM, Keejong

    IPC分类号： G11C29/02 ,  G11C29/50 ,  G11C29/14 ,  G11C7/02 ,  G11C11/419

    摘要： A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

    PSEUDO DUAL PORT MEMORY
    3.
    发明公开
    PSEUDO DUAL PORT MEMORY 有权
    PSEUDO双端口存储器

    公开(公告)号：EP3195318A1

    公开(公告)日：2017-07-26

    申请号：EP15748352.0

    申请日：2015-07-20

    申请人： Qualcomm Incorporated

    发明人： YOON, Sei Seung ,  KWOK, Tony Chung Yiu ,  JUNG, Changho ,  DESAI, Nishith Nitin

    IPC分类号： G11C7/10 ,  G11C8/16

    CPC分类号： G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

    摘要： A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

    摘要翻译： 存储器和操作提供的存储器的方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路被配置为响应访问周期的时钟的边沿来产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括一个锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

    DATA PROTECTION DURING POWER-UP IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY
    4.
    发明公开
    DATA PROTECTION DURING POWER-UP IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
    隐私，同时驾驶起来磁阻自旋转移力矩直接访问存储器

    公开(公告)号：EP2353165A1

    公开(公告)日：2011-08-10

    申请号：EP09752050.6

    申请日：2009-11-04

    申请人： QUALCOMM Incorporated

    发明人： YOON, Sei Seung ,  KANG, Seung H.

    IPC分类号： G11C11/16

    CPC分类号： G11C8/08 ,  G11C7/20 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675

    摘要： A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells (420-432), a power-up controller (405), and a first plurality of precharge transistors (410-413) is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines (BL) and word lines (WL). The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.

    IMPROVING MEMORY READ STABILITY USING SELECTIVE PRECHARGE OF BIT LINE SECTIONS
    5.
    发明公开
    IMPROVING MEMORY READ STABILITY USING SELECTIVE PRECHARGE OF BIT LINE SECTIONS 有权
    改善记忆读稳定性使用位线的选择性预充电

    公开(公告)号：EP2243140A1

    公开(公告)日：2010-10-27

    申请号：EP08862363.2

    申请日：2008-12-15

    申请人： QUALCOMM Incorporated

    发明人： ABU-RAHMA, Mohamed H. ,  CHABA, Ritu ,  CHEN, Nan ,  YOON, Sei Seung

    IPC分类号： G11C7/12

    CPC分类号： G11C11/419 ,  G11C7/02 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.

    CONTENT ADDRESSABLE MEMORY WITH MIXED SERIAL AND PARALLEL SEARCH
    7.
    发明公开
    CONTENT ADDRESSABLE MEMORY WITH MIXED SERIAL AND PARALLEL SEARCH 有权
    具有混合串行和并行搜索内容可寻址存储器

    公开(公告)号：EP1929481A1

    公开(公告)日：2008-06-11

    申请号：EP06825507.4

    申请日：2006-10-02

    申请人： Qualcomm Incorporated

    发明人： YOON, Sei Seung ,  JUNG, Seong-Ook

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C15/00

    摘要： A mixed serial-parallel content addressable memory (CAM) includes serial CAM cells and parallel CAM cells that are arranged in multiple (N) columns and multiple (M) rows. Each row includes at least one serial CAM cell and at least two parallel CAM cells. The M rows are searched in parallel. For each row, the serial CAM cells are searched sequentially, and the parallel CAM cells are selectively searched in parallel. The CAM further includes a driver that generates search lines for the N columns of CAM cells, one search line per column. The driver sets the search lines to an N-bit value to search for in the CAM. Prior to each search operation, the driver presets at least one search line for at least one column of serial CAM cells to precharge a match line for each row.