公开(公告)号：EP0177848A3

公开(公告)日：1988-01-13

申请号：EP85112234

申请日：1985-09-26

申请人： Honeywell Bull Inc.

发明人： Bradley, John J.

IPC分类号： G06F15/06 ,  G06F12/06

CPC分类号： G06F15/7842 ,  G06F1/22 ,  G06F12/0623

摘要： A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

公开(公告)号：EP0205081A2

公开(公告)日：1986-12-17

申请号：EP86107533.1

申请日：1986-06-03

申请人： Honeywell Bull Inc.

发明人： Carosso, Robert M.

IPC分类号： B41J3/00 ,  B41J25/20

CPC分类号： B41J25/20 ,  B41J3/01 ,  G06F17/215

摘要： ethod for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within the character set of the output device. The method provides for the vertical and/or horizontal offsetting of the printhead between the striking of individual characters which form the composite character.

摘要翻译： 一种通过在同一字符空间中多次识别两个或多个字符来在文字处理系统中打印复合字符的方法。 该方法允许通过使用在输出设备的字符集中发现的单独字符图形来生成复合字符图形。 该方法提供打印头在形成复合字符的单个字符的打击之间的垂直和/或水平偏移。

公开(公告)号：EP0082683A2

公开(公告)日：1983-06-29

申请号：EP82306732.7

申请日：1982-12-16

申请人： Honeywell Bull Inc.

发明人： Barlow, George J. ,  Nibby, Chester M., Jr. ,  Johnson, Robert B.

IPC分类号： G06F13/38 ,  G06F13/32

CPC分类号： G06F13/18 ,  G06F13/28

摘要： A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

公开(公告)号：EP0053487A1

公开(公告)日：1982-06-09

申请号：EP81305596.9

申请日：1981-11-26

申请人： Honeywell Bull Inc.

发明人： Keene, Bruce C. ,  Nielsen, Raymond E.

IPC分类号： G04F10/00 ,  H03K3/288

CPC分类号： G04F10/00

摘要： Test apparatus enables the relative timing of two signals picked up by probes 16, 18 to be determined. The two signals are fed, via switchable polarity and level changing circuitry 10, 11, 13,14 to a simple flip-flop 12, which comprises two cross-coupled transistors plus two input transistors. With both inputs at 0, the flip-flop is in an abnormal state with both cross-coupled flip-flops in the same state. The first input signal to go to 1 causes the flip-flop to enter a corresponding one of its two normal states (the cross-coupled flip-flops in opposite states). Detection circuitry 24 and display means 15 signal this state.
A low frequency bias oscillator 20 shifts the sloping transitions of one signal up and down relative to the other, changing their relative timing. For a part of each slow cycle dependent on the relative timings of the two signals, their effective timings at the flip-flop will be reversed. Hence the mean output from 24 will be dependent on the time difference between the two signals.

摘要翻译： 测试装置能够确定由探头16,18拾取的两个信号的相对定时。 两个信号通过可切换极性和电平改变电路10,11,13,14馈送到简单的触发器12，其包括两个交叉耦合晶体管和两个输入晶体管。 当两个输入为0时，触发器处于异常状态，两个交叉耦合触发器处于相同的状态。 要进入1的第一个输入信号使触发器进入其两个正常状态中的相应的一个（交叉耦合的触发器处于相反的状态）。 检测电路24和显示装置15发信号通知该状态。 低频偏置振荡器20相对于另一个信号上下移动一个信号的倾斜转变，改变它们的相对定时。 对于每个慢周期的一部分，取决于两个信号的相对定时，它们在触发器的有效定时将被反转。 因此，24的平均输出将取决于两个信号之间的时间差。

公开(公告)号：EP0049627A2

公开(公告)日：1982-04-14

申请号：EP81304592.9

申请日：1981-10-05

申请人： Honeywell Bull Inc.

发明人： Holtey, Thomas O. ,  Raymond, James C. ,  Noyes, Steven S.

IPC分类号： H04L7/10 ,  G06F13/42

CPC分类号： H04L7/042

摘要： The circuitry synchronizes byte boundaries in a serial bit stream from a communications processor 10 with a byte timing signal BYTE from a device 26, the signal BYTE being in synchronism with bit timing pulses CLK but not byte boundaries. The bit stream starts with two all 1's bytes and an all 0's byte. The number of 1's in the second all 1's pulse following the BYTE signal is counted by a counter 200; the data bit stream is fed into a shift register 202; and the appropriate output is selected by a multiplexer 204 controlled by the stored count in counter 200, to achieve synchronization.
The unit 10 may be coupled to several devices 20, 22, 26 having differently timed BYTE signals, with the count from the counter in the active adapter 12, 14, 20 being fed to unit 10 to identify the active one of the devices.

摘要翻译： 该电路使来自通信处理器10的串行比特流中的字节边界与来自设备26的字节定时信号BYTE同步，该信号BYTE与比特定时脉冲CLK同步而不是字节边界。 位流以两个全1的字节和全0的字节开始。 在BYTE信号之后的第二个全1脉冲中的1的数目由计数器200计数; 数据比特流被馈送到移位寄存器202中; 并且由计数器200中存储的计数控制的多路复用器204选择适当的输出，以实现同步。 单元10可以耦合到具有不同定时的BYTE信号的多个设备20,22,26，来自主动适配器12,14,20中的计数器的计数被馈送到单元10以识别活动的一个 的设备。

公开(公告)号：EP0049158A2

公开(公告)日：1982-04-07

申请号：EP81304501.0

申请日：1981-09-29

申请人： Honeywell Bull Inc.

发明人： Yu, Kin C. ,  Goss, Gary J.

IPC分类号： G06F13/42 ,  G06F15/16

CPC分类号： G06F13/24 ,  G06F13/385 ,  G06F15/167

摘要： A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The 1/0 microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory 44. The line microprocessor is controlled by a PROM 58 and channel control programms (CCP's) in a RAM 60, and uses a work RAM 52 for data storage; the 1/0 microprocessor is controlled by a PROM 38 and uses a work RAM 40 for data storage. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

摘要翻译： 数据处理系统包括具有用于与中央处理单元和主存储器通信的I / O微处理器的通信子系统; 以及用于与多个设备通信的线路微处理器。 I / O微处理器和线路微处理器通过存储在共享存储器44中的邮箱彼此进行通信。线路微处理器由RAM60中的PROM58和通道控制程序（CCP）控制，并且使用工作RAM 52 数据存储; I / O微处理器由PROM 38控制，并且使用工作RAM40进行数据存储。 线路微处理器中断I / O微处理器以处理在主存储器和请求服务的设备之间传输的数据字节，当线路微处理器响应请求设备并加载邮箱时。

公开(公告)号：EP0255090A3

公开(公告)日：1990-02-07

申请号：EP87110864.3

申请日：1987-07-27

申请人： Honeywell Bull Inc.

发明人： Beauchemin, Edward

IPC分类号： G06F15/16 ,  H04L11/16

CPC分类号： G06F13/128 ,  G06F13/4027 ,  H04L12/46 ,  H04L29/00

摘要： A local area network (LAN) controller proprietary bus is disclosed comprised of a multiprocessor (µP) bus, a direct memory access bus, and an adapter bus. The bus permits the attachment of various computer elements while providing other integrity and communication functions to other computer elements or computer systems beyond the bus. The proprietary bus includes an adapter interface having up to four daughterboards. Each daughterboard has odd and even numbered connectors. Certain daughterboards are designed to handle control lines; whereas other daughterboards handle data and address lines. These daughterboards are the hardware means by which communications with LANs which are attached to the proprietary bus are accomplished with processes, disks, tapes, memories, attached to the proprietary bus.

摘要翻译： 公开了一种局域网（LAN）控制器专用总线，其包括多处理器（mu P）总线，直接存储器存取总线和适配器总线。 总线允许各种计算机元件的附接，同时向总线之外的其他计算机元件或计算机系统提供其他完整性和通信功能。 专有总线包括一个具有多达四个子板的适配器接口。 每个子板有奇数和偶数编号的连接器。 某些子板设计用于处理控制线; 而其他子板处理数据和地址行。 这些子板是与连接到专有总线的LAN进行通信的硬件装置，通过连接到专用总线的进程，磁盘，磁带，存储器来完成。

公开(公告)号：EP0273136A3

公开(公告)日：1989-10-25

申请号：EP87115987.7

申请日：1987-10-30

申请人： Honeywell Bull Inc.

发明人： Klashka, John A. ,  Kaufman, Sidney L. ,  Kowal, Krzysztof A. ,  Lewis, Richard P. ,  Raisbeck, Susan L. ,  McNamara, John L.

IPC分类号： G06F13/10 ,  G06F13/36 ,  G06F15/16 ,  G06F9/44

CPC分类号： G06F15/177 ,  G06F13/385

摘要： In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.

公开(公告)号：EP0077147B1

公开(公告)日：1989-08-16

申请号：EP82305138.8

申请日：1982-09-29

申请人： Honeywell Bull Inc.

发明人： Wilder, Richard P., Jr.

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F11/349

公开(公告)号：EP0311706A1

公开(公告)日：1989-04-19

申请号：EP87115020.7

申请日：1987-10-14

申请人： Honeywell Bull Inc.

发明人： Abraham, Ronald Frank

IPC分类号： H05K7/14 ,  H01R23/70

CPC分类号： H01R12/57 ,  H05K7/1457

摘要： A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element and the second element. The apparatus comprises a shaft, having a first, second, and third diameter along the axis of the shaft, thereby forming a first, second, and third shaft, respectively, the first diameter being the smallest diameter and the third diameter being the largest diameter. The first shaft is threaded, for mating with the second element. A spring, having an inside diameter smaller than the diameter of the third shaft and having a length approximately equal to the length of the first and second shaft is coaxially positioned over the first and second shaft. When the first element is placed in contact with the second element, there is applied a minimum predetermined force between the first and second element by the action of the spring when the first shaft is inserted into the hole of the second element to the point where the base of the second shaft contacts the surface of the first element.

摘要翻译： 配电系统的螺栓构造利用将第一元件连接到第二元件的装置，第二元件具有孔，使得在第一元件和第二元件之间的连接处存在最小预定力。 该装置包括轴，沿着轴的轴线具有第一，第二和第三直径，从而分别形成第一，第二和第三轴，第一直径为最小直径，第三直径为最大直径 。 第一轴是螺纹的，用于与第二元件配合。 具有比第三轴的直径小的内径并且具有大致等于第一和第二轴的长度的长度的弹簧同轴地定位在第一和第二轴上方。 当第一元件与第二元件接触时，当第一轴插入到第二元件的孔中时，通过弹簧的作用在第一和第二元件之间施加最小的预定力， 第二轴的基部接触第一元件的表面。