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    LDPC decoder for decoding a low-density parity check (LDPC) codewords
    51.
    发明公开
    LDPC decoder for decoding a low-density parity check (LDPC) codewords 审中-公开
    迪士尼公司的迪士尼公司

    公开(公告)号：EP1610466A1

    公开(公告)日：2005-12-28

    申请号：EP05012044.3

    申请日：2005-06-03

    申请人： Infineon Technologies AG

    发明人： Litsyn, Simon ,  Sharon, Eran

    IPC分类号： H03M13/11 ,  H04L1/00

    CPC分类号： H04L1/005 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/3738 ,  H03M13/618 ,  H03M13/635 ,  H04L1/0057 ,  H04L1/0068

    摘要： LDPC decoder which comprises:

    (a) a memory (3) for storing for each codeword bit of the received noisy codeword (Y) a priori estimates (Qv) that said codeword bit has a predetermined value from the received noisy codeword (Y) and from predetermined parameters of the communication channel;
    (b) generalized check node processing units (5) for calculating iteratively messages on all edges of said bipartite graph according to a serial schedule
    wherein in each iteration, for each check node (C) of said bipartite graph, for all neighboring variable nodes (V) connected to said check node (C) input messages (Q VC ) to said check node (C) from said neighboring variable nodes (V) and output messages (R CV ) from the check node (C) to said neighboring variable nodes (V) are calculated by means of a message passing computation rule.

    摘要翻译： LDPC解码器，其包括：（a）存储器（3），用于存储所接收的噪声码字（Y）的每个码字比特，所述先验估计（Qv）所述码字比特具有来自所接收的噪声码字（Y）的预定值，以及 来自通信信道的预定参数; （b）广义校验节点处理单元（5），用于根据串行调度在所述二分图的所有边缘上迭代地计算消息，其中在针对所有相邻变量节点（对于所述二分图的每个校验节点（C））的每次迭代中 （C）将来自所述相邻可变节点（V）的所述校验节点（C）的输入消息（QVC）和从所述校验节点（C）到所述相邻变量节点（V）的输出消息（RCV）连接到所述校验节点 ）通过消息传递计算规则计算。

    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO
    56.
    发明公开
    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO 审中-实审

    公开(公告)号：EP4358416A2

    公开(公告)日：2024-04-24

    申请号：EP24160345.5

    申请日：2018-11-07

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： LIU, Qingchao ,  CHEN, Xixian ,  NEZAMI, Yashar

    IPC分类号： H03M13/11

    CPC分类号： H03M13/116 ,  H03M13/2707 ,  H03M13/635 ,  H03M13/6561 ,  H03M13/6569 ,  H03M13/13

    摘要： Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

    PARALLEL PROCESSING METHOD OF BIT RATE MATCHING AND DEVICE THEREOF
    60.
    发明公开
    PARALLEL PROCESSING METHOD OF BIT RATE MATCHING AND DEVICE THEREOF 审中-公开
    位速率匹配的并行处理方法及其装置

    公开(公告)号：EP3193452A1

    公开(公告)日：2017-07-19

    申请号：EP17155831.5

    申请日：2010-09-28

    申请人： ZTE Corporation

    发明人： Wang, Weitao ,  Zhen, Shouhong

    IPC分类号： H03M13/00 ,  H04L1/00 ,  H03M13/27

    CPC分类号： H03M13/271 ,  H03M13/2792 ,  H03M13/635 ,  H03M13/6525 ,  H03M13/6561 ,  H04L1/0068 ,  H04L1/0071

    摘要： A parallel processing method of bit rate matching and an apparatus thereof are disclosed in the present invention. In the parallel processing method, interleaving processing is performed on N system bit data in the system bit data stream to be cached in parallel in the storage used for storing the system bit data, and interleaving processing is performed on N corresponding data groups in the check 1 data stream and the check 2 data stream to be cached in parallel in the storage used for storing the check data.

    摘要翻译： 在本发明中公开了一种比特率匹配的并行处理方法及其装置。 在并行处理方法中，对系统比特数据流中的N个系统比特数据进行交织处理，以并行缓存在用于存储系统比特数据的存储器中，并且对检查中的N个对应数据组执行交织处理 1数据流和检查2数据流并行地缓存在用于存储检查数据的存储器中。