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    HYBRID MEMORY MANAGEMENT
    52.
    发明公开
    HYBRID MEMORY MANAGEMENT 审中-公开
    混合内存管理

    公开(公告)号：EP3291097A2

    公开(公告)日：2018-03-07

    申请号：EP17185832.7

    申请日：2017-08-11

    申请人： Google LLC

    发明人： Coburn, Joel Dylan ,  Borchers, Albert ,  Johnson, Christopher Lyle ,  Sprinkle, Robert S.

    IPC分类号： G06F12/0802 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/0868 ,  G06F12/0831

    CPC分类号： G06F3/0685 ,  G06F3/0619 ,  G06F3/065 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0868 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

    摘要： Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

    摘要翻译： 用于基于利用至少一个页面表漫游器扫描页面表来确定是否为页表的每个页表项设置访问位的方法，系统和装置，所述访问位指示与页面关联的页面 表条目在最后一个扫描周期被访问; 响应于确定为与所述页面相关联的页面表条目设置了访问位，递增每个页面的计数; 在确定是否为每个页表条目设置访问位之后重置访问位; 从主存储器接收访问第一页数据的请求; 基于确定第一页数据未存储在主存储器中来启动页面错误; 并用DMA引擎来处理页面错误。

    TWO STAGE COMMAND BUFFERS TO OVERLAP IOMMU MAP AND SECOND TIER MEMORY READS
    53.
    发明公开
    TWO STAGE COMMAND BUFFERS TO OVERLAP IOMMU MAP AND SECOND TIER MEMORY READS 审中-公开
    两阶段命令缓冲区重叠IOMMU MAP和第二层存储器读取

    公开(公告)号：EP3270293A1

    公开(公告)日：2018-01-17

    申请号：EP17179008.2

    申请日：2017-06-30

    申请人： Google LLC

    发明人： SHAH, Monish ,  SEREBRIN, Benjamin Charles ,  BORCHERS, Albert

    IPC分类号： G06F12/08 ,  G06F12/1081 ,  G06F12/0868 ,  G06F13/28

    摘要： IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.

    摘要翻译： IOMMU映射可能与第二层存储器访问重叠，使得两个操作至少部分同时执行。 例如，当第二层存储器读入存储设备控制器内部缓冲器时，可以同时建立IOMMU映射。 为了实现这种重叠，使用两级命令缓冲区。 在第一阶段，将内容从第二层存储器地址读入存储设备控制器内部缓冲区。 在第二阶段，内部缓冲区被写入DRAM物理地址。

    SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT
    55.
    发明公开
    SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT 审中-公开

    公开(公告)号：EP4280073A3

    公开(公告)日：2024-02-21

    申请号：EP23187251.6

    申请日：2020-01-31

    申请人： INTEL Corporation

    发明人： Shanbhogue, Vedvyas ,  Chhabra, Siddhartha ,  Harriman, David J. ,  Makaram, Raghunandan ,  Schoinas, Ioannis T.

    IPC分类号： H04L9/40 ,  G06F12/1081 ,  G06F21/64 ,  G06F21/60 ,  G06F13/42

    摘要： Methods, systems, and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed. An apparatus comprises a first device comprising circuitry to, using an end-to-end protocol, secure a transaction in a first secure stream based at least in part on a transaction type of the transaction, where the first secure stream is separate from a second secure stream. The first device is further to send the transaction secured in the first secure stream to a second device over a link established between the first device and the second device, where the transaction is to traverse one or more intermediate devices from the first device to the second device. In more specific embodiments, the first secure stream is based on one of a posted transaction type, a non-posted transaction type, or completion transaction type.