公开(公告)号：EP1230589A4

公开(公告)日：2008-03-19

申请号：EP01967928

申请日：2001-05-07

申请人： LEE RUBY B

发明人： LEE RUBY B ,  YANG XIAO

IPC分类号： G06F7/24 ,  G06F7/76 ,  G06F9/30 ,  G06F9/308 ,  G06F9/315 ,  G09C1/00 ,  H04L29/06 ,  G06F7/38

CPC分类号： G06F7/762 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  H04L9/0618 ,  H04L63/04 ,  H04L63/0428 ,  H04L63/0435 ,  H04L2209/122

摘要： The present invention provides permutation instructions which can be used in software executed in a programmable processor (14) for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on an omega-flip network comprising at least two stages in which each stage can perform the function of either an omega network stage or a flip network stage. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permuting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits.

公开(公告)号：EP1857926A1

公开(公告)日：2007-11-21

申请号：EP06126516.1

申请日：2006-12-19

申请人： International Business Machines Corporation

发明人： Greiner, Dan

IPC分类号： G06F9/315

CPC分类号： G06F9/30003 ,  G06F9/30032 ,  G06F12/1475 ,  G11C8/20

摘要： Use of storage access keys is facilitated to enable flexible control of storage access. Any selected storage access key is usable to access storage. Storage access keys may be specified in user registers and can override storage access keys indicated in system registers.

摘要翻译： 便于使用存储访问密钥来实现对存储访问的灵活控制。 任何选定的存储访问密钥都可用于访问存储。 存储访问密钥可以在用户注册中指定，并且可以覆盖系统寄存器中指示的存储访问密钥。

公开(公告)号：EP1828884A2

公开(公告)日：2007-09-05

申请号：EP05824323.9

申请日：2005-12-13

申请人： Koninklijke Philips Electronics N.V.

发明人： GRUIJTERS, Paulus W.,F. ,  QUAX, Marcus, M.,G. ,  HELD, Ingolf

IPC分类号： G06F9/315 ,  G06F9/312 ,  G06F9/308 ,  G06F9/305 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

公开(公告)号：EP1242869A4

公开(公告)日：2006-10-25

申请号：EP00959713

申请日：2000-08-31

申请人： INTEL CORP

发明人： WOLRICH GILBERT ,  ADILETTA MATTHEW J ,  WHEELER WILLIAM ,  BERNSTEIN DEBRA ,  HOOPER DONALD

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (CONTEXT). The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts (Context Descriptors) are also disclosed.

公开(公告)号：EP1236097A4

公开(公告)日：2006-08-02

申请号：EP00959712

申请日：2000-08-31

申请人： INTEL CORP

发明人： WOLRICH GILBERT ,  ADILETTA MATTHEW J ,  WHEELER WILLIAM ,  BERNSTEIN DEBRA ,  HOOPER DONALD

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

公开(公告)号：EP1236094A4

公开(公告)日：2006-04-19

申请号：EP00961457

申请日：2000-08-31

申请人： INTEL CORP

发明人： WOLRICH GILBERT ,  ADILETTA MATTHEW J ,  WHEELER WILLIAM ,  BERNSTEIN DEBRA ,  HOOPER DONALD

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/32

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

摘要： A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.

公开(公告)号：EP1620790A2

公开(公告)日：2006-02-01

申请号：EP04722539.6

申请日：2004-03-23

申请人： Infineon Technologies AG

发明人： NIE, Xiaoning ,  WAHL, Thomas

IPC分类号： G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30032

摘要： The invention relates to a method and a program-controlled unit for displacing bit fields in a storage device of a program-controlled unit as a result of a command being executed, by means of which a bit segment is displaced within a first storage unit into a second storage unit. Said method comprises the following steps: a) the bit segment having a first bit width is read out from a first bit field of the first storage unit, beginning at a first starting point; b) the read-out bit segment is stored in a first bit field of the second storage unit, beginning at a second starting point; c) the first and/or the second starting point is/are updated by a given value; d) the updated first and/or second starting point is/are stored for subsequent steps.

摘要翻译： 本发明涉及一种方法和一种程序控制单元，用于作为正在执行的命令的结果来移位程序控制单元的存储设备中的位字段，通过该方法在第一存储单元内将位段移位成 第二存储单元。 所述方法包括以下步骤：a）从第一起始点开始，从第一存储单元的第一位字段中读出具有第一位宽的位段; b）读出位段存储在第二存储单元的第一位字段中，从第二起始点开始; c）以给定值更新第一和/或第二起始点; d）为后续步骤存储更新的第一和/或第二起始点。

公开(公告)号：EP1612661A2

公开(公告)日：2006-01-04

申请号：EP05253896.4

申请日：2005-06-23

申请人： INTEL CORPORATION

发明人： Saha, Bratin ,  Merten, Matthew ,  Hammarlund, Per

IPC分类号： G06F9/315

CPC分类号： G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

摘要： A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

摘要翻译： 提供了一种使用睡眠 - 唤醒机制​​进行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。

公开(公告)号：EP1508853A1

公开(公告)日：2005-02-23

申请号：EP03255133.5

申请日：2003-08-19

申请人： STMicroelectronics Limited ,  Hewlett-Packard Company

发明人： Homewood, Fred ,  Faraboschi, Paolo

IPC分类号： G06F9/312 ,  G06F9/315 ,  G06F9/30 ,  G06F12/04

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/30145 ,  G06F12/04

摘要： A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.

摘要翻译： 一种从存储器中的指定的未对齐字地址加载未对齐字的方法，所述未对齐字包括与字边界交叉的多个索引部分，所述方法包括：从对应的字地址加载第一对齐字， 未对齐的字地址; 识别表示所述未对齐字地址相对于对齐的字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 以及使用所识别的索引来组合第一和第二对齐字的索引部分以构造未对齐字。

公开(公告)号：EP1387251A2

公开(公告)日：2004-02-04

申请号：EP03291912.8

申请日：2003-07-30

申请人： Texas Instruments Incorporated ,  Texas Instruments France

发明人： Chauvel, Gerard ,  Lasserre, Serge

IPC分类号： G06F9/315 ,  G06F9/312 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F9/30134 ,  G06F9/30101 ,  G06F9/30174 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/502

摘要： A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's core. The local data stack is coupled to the main stack and is located internal to the processor's core. The local data stack has a plurality of entries that correspond to entries in the main stack. Each flag is associated with a corresponding entry in the local data stack and indicates whether the data in the corresponding local data stack entry is valid. The system performs two instructions. One instruction synchronizes the main stack to the local data stack and invalidates the local data stack, while the other instruction synchronizes the main stack without invalidating the local data stack.