公开(公告)号：EP4254197A1

公开(公告)日：2023-10-04

申请号：EP23156438.6

申请日：2023-02-14

申请人： INTEL Corporation

发明人： Merten, Matthew ,  Strong, Beeman ,  Cohen, Moshe ,  Yasin, Ahmad ,  Kleen, Andreas ,  Bratanov, Stanislav ,  Gopalakrishnan, Karthik ,  Schmid, Angela ,  Zhou, Grant

IPC分类号： G06F11/30 ,  G06F11/34 ,  G06F11/36

摘要： Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：EP1612661A2

公开(公告)日：2006-01-04

申请号：EP05253896.4

申请日：2005-06-23

申请人： INTEL CORPORATION

发明人： Saha, Bratin ,  Merten, Matthew ,  Hammarlund, Per

IPC分类号： G06F9/315

CPC分类号： G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

摘要： A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

摘要翻译： 提供了一种使用睡眠 - 唤醒机制​​进行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。

公开(公告)号：EP3716057A1

公开(公告)日：2020-09-30

申请号：EP20153754.5

申请日：2020-01-27

申请人： INTEL Corporation

发明人： Dechene, Mark ,  Srinivasan, Srikanth ,  Merten, Matthew ,  Christiansen, Ammon

IPC分类号： G06F9/38

摘要： A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

公开(公告)号：EP1612661A3

公开(公告)日：2007-09-19

申请号：EP05253896.4

申请日：2005-06-23

申请人： INTEL CORPORATION

发明人： Saha, Bratin ,  Merten, Matthew ,  Hammarlund, Per

IPC分类号： G06F9/315 ,  G06F9/46

CPC分类号： G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

摘要： A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.