公开(公告)号：EP1623504A2

公开(公告)日：2006-02-08

申请号：EP04760349.3

申请日：2004-04-23

Applicant: QUALCOMM INCORPORATED

Inventor： BURKE, Joseph, Patrick

IPC: H03M1/00

CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M3/504 ,  H04B1/71635

Abstract: An electronic circuit for processing a digital signal may include a plurality of digital delay circuits, each configured to produce a delayed replica of the digital signal; a plurality of digital-to-analog converters, each configured to convert the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits, each configured to adjust the analog signal from one of the digital-to-analog converters by a gain factor and each having an output; and an analog summer configured to sum the outputs of the analog gain circuits. The number of delay circuits and the magnitude of the delays and gains may be selected to cause the circuit to function as a band pass filter, a high pass filter, a low-pass filter, a notch filter, or any other type of filter. The circuit may be used in a broad variety of applications, including a transceiver (such as a subscriber station) and in ultra wideband applications.

公开(公告)号：EP1384327A4

公开(公告)日：2005-12-07

申请号：EP02728988

申请日：2002-04-25

Applicant: CIRRUS LOGIC INC

Inventor： TUCKER JOHN CHRISTOPHER

IPC: H03M3/02 ,  H03M3/04 ,  H03M3/00 ,  H03M1/00

CPC classification number: H03M3/32 ,  H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M3/454

Abstract: A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital ("A/D) converter. A first, upstream integrator is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply. The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain k1 for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain k2 for a second integrator is set to have a sufficiently small value so that an output voltage from the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.

公开(公告)号：EP1593201A2

公开(公告)日：2005-11-09

申请号：EP04707478.6

申请日：2004-02-03

Applicant: Infineon Technologies AG

Inventor： HERNDL, Thomas ,  BERKMANN, Jens

IPC: H03M1/00

CPC classification number: H03M13/2957 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2789 ,  H04L1/0043 ,  H04L1/0066

Abstract: According to the invention, a pair of coordinates (c1, r1) of a rectangular matrix is calculated for a certain index k of an interleaved or deinterleaved sequence of symbols. Said pair of coordinates is corrected so as to take into account fillers in the rectangular matrix. A transformed pair of coordinates (c6, r6) is determined for the corrected pair of coordinates (c4, r5) by means of a matrix coordinate transformation (T1) process. A valid interleaving address or deinterleaving address I (k) is then calculated from the transformed pair of coordinates (c6, r6) at a timing step k.

公开(公告)号：EP1570576A2

公开(公告)日：2005-09-07

申请号：EP03776059.2

申请日：2003-12-05

Applicant: LG ELECTRONICS INC.

Inventor： LEE, Koon Seok ,  KIM, Yong Tae ,  BAEK, Seung Myun

IPC: H03M1/00

CPC classification number: H04L63/065 ,  H04L12/2803 ,  H04L12/2807 ,  H04L2012/2841 ,  H04L2012/2843 ,  H04L2012/285

Abstract: Disclosed is method for setting a home code of a home network system, the method including the steps of: creating the home code of the first adaptor; determining whether or not the home code is duplicated; and if the home code is not duplicated, setting the home code of the first adaptor to the second adaptor.

公开(公告)号：EP1552615A1

公开(公告)日：2005-07-13

申请号：EP03808941.3

申请日：2003-07-29

Applicant: ANALOG DEVICES, INC.

Inventor： CARREAU, Gary ,  AMAZEEN, BRUCE

IPC: H03M1/00

CPC classification number: H03M1/1245 ,  H03M1/468

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched­capacitor circuit comprises a plurality of capacitors arranged according to several embodiments

公开(公告)号：EP1550220A1

公开(公告)日：2005-07-06

申请号：EP03798325.1

申请日：2003-09-17

Applicant: Koninklijke Philips Electronics N.V.

Inventor： LI, Qiong ,  GIANNOPOULOS, Demetri

IPC: H03M1/00 ,  H03L7/18 ,  H03M1/10 ,  H03G3/20 ,  G01C19/70

CPC classification number: G05B21/02

Abstract: A digital controller comprises two control paths each having an A/D converter. One of the two converters has a substantially higher sampling speed and lower resolution than the other. Thus, one is suitable to deal with the fast responses while the other is suitable to deal with the slow responses, and can replace high-speed high-resolution A/D converter which is high in both cost and power consumption.

公开(公告)号：EP1479168A1

公开(公告)日：2004-11-24

申请号：EP01912986.5

申请日：2001-02-23

Applicant: Rzyski, Eugene

Inventor： Rzyski, Eugene

IPC: H03M1/00

CPC classification number: H04L27/24 ,  H04L27/10 ,  H04L27/34

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal (3) is converted into a digital signal (6) by an analog-to-digital converter (5). The digital signal (6) is then converted into an analog signal having an alternating frequency (13) by a first converter processor (7) and an alternating frequency generator (11) according to a predetermined conversion table (9). To reproduce the original analog signal (3), the analog signal having an alternating frequency (13) is first converted back into a digital signal (6) by an alternating frequency measurement means (21) connected to a second converter processor (23), also in accordance with the predetermined conversion table (9). The digital signal (6) is then converted to the original analog signal (3) by a digital-to-analog converter (25).

公开(公告)号：EP1464147A2

公开(公告)日：2004-10-06

申请号：EP02781727.9

申请日：2002-12-11

Applicant: Agere Systems (Ireland) Research Limited

Inventor： MOLINA NAVARRO, Alberto ,  BATES, Stephen ,  CURRAN, Philip ,  MURRAY, Carl Damien

IPC: H04L25/02 ,  H04L25/14 ,  H03M1/00 ,  H04L7/02

CPC classification number: H04L7/0029 ,  H04L25/14 ,  H04L2025/03484

Abstract: A Gigabit transceiver (1) has a receiver (2) and a transmitter (3). There is an ADC (5) in the receiver (2) for each channel (A, B, C, D). The ADCs (5) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs (2) operate off half of the oversampling rate. In the receiver (2) fractionally spaced equalisers (FSEs, 6) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

公开(公告)号：EP1137232A3

公开(公告)日：2004-07-14

申请号：EP01107228.7

申请日：2001-03-22

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Orihashi, Masayuki ,  Abe, Katsuaki ,  Msuya, Job Cleopa ,  Takabayashi, Shinichiro

IPC: H04L27/38 ,  H04L27/22 ,  H04L27/08 ,  H04L27/00 ,  H03M1/00 ,  H03D3/00

CPC classification number: H03D3/006 ,  H04L27/2647

Abstract: A signal transmitted from a transmitting-side apparatus is received, through a propagation path, in receiving section 101 in a digital reception apparatus illustrated in FIG. 1. A signal 150 (received signal) received in receiving section 101 is amplified in amplifying section 102 to be an amplified signal 151. The amplified signal 151 is output to distortion estimating section 103a and distortion compensating section 103b in distortion correcting section 103. Distortion estimating section 103a has information on the distortion characteristic of amplifying section 102 input beforehand thereto. Distortion estimating section 103a estimates a distortion component contained in the amplified signal 151, using the information on the distortion characteristic of amplifying section 102 and the amplified signal 151 from amplifying section 102. Further, using the estimated distortion component, the section 103a generates a correcting signal 152 to correct the distortion component of the amplified signal 151. Distortion estimating section 103a is comprised of, for example, an element having the inverse characteristic of a section where the resultant signal needs the correction (in this case, amplifying section 102). The correcting signal 152 generated in distortion estimating section 103a is output to distortion compensating section 103b. Distortion compensating section 103b multiplies the amplified signal 151 from amplifying section 102 by the correcting signal 152 from distortion estimating section 103a. A corrected amplified signal 153 is thereby obtained which equals the amplified signal 151 from which the distortion component is removed. The obtained corrected amplified signal 153 is output to demodulating section 104. Demodulating section 104 performs the demodulation processing on the corrected amplified signal 153, and thereby obtains a demodulated signal 154.

公开(公告)号：EP1104196A3

公开(公告)日：2004-06-16

申请号：EP00308590.9

申请日：2000-09-29

Applicant: Denon, Ltd.

Inventor： Ushirogi, Shingo

IPC: G11B20/12 ,  H03M7/30 ,  H03M1/00

CPC classification number: H04N19/59 ,  G10L19/24

Abstract: There is provided a data storage device concurrently allowing storage of data that can be reproduced in higher quality and storage of data that can be used also in a data transmission path with a lower transfer speed. The data storage device comprises an A/D converter 103 for sampling analog audio signals based on a sampling frequency, a DSP 104 for compressing sample data sequentially output from the A/D converter 103, a storing and reading control unit 107 for storing the compressed data sequentially output from the DSP 104, and a control unit 105 for controlling the DSP 104 and the storing and reading control unit 107 for dividing the sample data sequentially output from the A/D converter 103 into a group under odd number of turns and a group under even number of turns, compressing the groups at each different compression rate and storing them on different storage areas A and B, respectively.