公开(公告)号：EP3186888B1

公开(公告)日：2021-05-05

申请号：EP15857050.7

申请日：2015-11-06

发明人： ALEXANDER, William C.

IPC分类号： H03K17/66 ,  H03K17/687 ,  H02M3/158

公开(公告)号：EP3051646B1

公开(公告)日：2020-02-26

申请号：EP16152390.7

申请日：2016-01-22

申请人： General Electric Company

发明人： TENCA, Pierluigi ,  SIHLER, Christof Martin

IPC分类号： H02H7/26 ,  H01H33/59 ,  H03K17/08 ,  H02J1/10 ,  H02J3/38 ,  H03K17/66 ,  H02H3/087 ,  H02H3/20

公开(公告)号：EP3270513B1

公开(公告)日：2019-07-03

申请号：EP16305876.1

申请日：2016-07-11

申请人： NXP USA, Inc.

发明人： Sicard, Thierry

IPC分类号： H03K17/66 ,  H03K17/16

公开(公告)号：EP3270513A1

公开(公告)日：2018-01-17

申请号：EP16305876.1

申请日：2016-07-11

申请人： NXP USA, Inc.

发明人： Sicard, Thierry

IPC分类号： H03K17/66 ,  H03K17/16

CPC分类号： H03K17/08116 ,  H01L29/7393 ,  H03K17/163 ,  H03K17/168

摘要： A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.

摘要翻译： 提供了一种方法和设备，用于通过在关断时间将关断电压施加到驱动端子来控制功率晶体管的驱动端子，测量驱动端子处的栅极电流以检测预定的栅极电流斜率，确定 在检测到所述预定栅极电流斜率的关断时间之后的第一时间增量，确定与所述第一时间增量成比例并且在所述功率晶体管的米勒平台内期满的第二时间增量，并且将所述栅极电流降低至 驱动端子在第二时间增量期满时达到预定的电流水平，以便降低功率晶体管处的过电压。

公开(公告)号：EP3186888A4

公开(公告)日：2018-01-17

申请号：EP15857050

申请日：2015-11-06

申请人： IDEAL POWER INC

发明人： ALEXANDER WILLIAM C

IPC分类号： H03K17/66 ,  H02M3/158 ,  H03K17/687

CPC分类号： H03K17/66 ,  H01L27/0694 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7412 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/872 ,  H02M1/08 ,  H02M7/219 ,  H02M2007/2195 ,  H03K17/60 ,  H03K17/602 ,  H03K17/687 ,  H03K2217/0054

摘要： The present application teaches, among other innovations, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment). (The B-TRAN, unlike other bipolar junction transistors, is controlled by applied voltage rather than applied current.) The preferred implementation of the drive circuit is operated by control signals to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with a low voltage drop (the “transistor-ON” state). In some but not necessarily all preferred embodiments, an adjustable low voltage for the gate drive circuit is provided by a self-synchronizing rectifier circuit. Also, in some but not necessarily all preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while the base current at that terminal is monitored, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

公开(公告)号：EP1956709A3

公开(公告)日：2013-03-27

申请号：EP08000991.3

申请日：2008-01-19

申请人： SEMIKRON Elektronik GmbH & Co. KG

发明人： Herzer, Reinhard, Dr. ,  Roßberg, Matthias ,  Vogler, Bastian

IPC分类号： H03K17/0812 ,  H03K19/0185 ,  H03K17/66

CPC分类号： H03K17/08122 ,  H03K17/666 ,  H03K19/018521

摘要： Die Erfindung beschreibt eine Ansteuerschaltung in leistungselektronischen Systemen mit einer Halbbrückenschaltung von zwei Leistungsschaltern, einem ersten sog. TOP-Schalter und einem zweiten sog. BOT- Schalter, die in einer Reihenschaltung angeordnet sind. Die Ansteuerschaltung weist einen TOP- Levelshifter zur Übertragung eines Eingangssignals von einer Ansteuerlogik zu einem TOP- Treiber auf. Hierbei ist der TOP- Levelshifter ausgebildet ist als eine Anordnung eines UP- und eines DOWN-Levelshifterzweiges sowie einer nachgeschalteten Signalauswerteschaltung. In dem zugeordneten Verfahren zur Übertragung dieses Eingangssignals übergibt die Signalauswerteschaltung ein Ausgangssignal an den TOP- Treiber, wenn entweder der UP- oder der DOWN-oder beide Levelshifterzweige ein Signal an den jeweils zugeordneten Eingang der Signalauswerteschaltung abgeben.

公开(公告)号：EP1035651A3

公开(公告)日：2003-11-05

申请号：EP00200834.0

申请日：2000-03-08

申请人： Texas Instruments Incorporated

发明人： Fukui, Eizo

IPC分类号： H03K17/66

CPC分类号： H03K17/16 ,  H03K17/667 ,  H03K2217/0036

摘要： To realize a driving circuit and a charging pump booster circuit utilizing said [driving circuit] capable of reducing the power consumption and the noise generated during switching. Transistors Q1 and Q2 are controlled based on a control signal input into an input terminal T in , and a charge/discharge current is output to an output terminal T out . The base of a transistor Q5, having almost the same characteristics as those of the transistor Q1, is connected to the base of the transistor Q1 in order to have the transistor Q5 generate a current corresponding to the turning on/off of the transistor Q1, and the current from said transistor Q5 is reflected toward a resistance element R1 by means of a current mirror circuit comprising transistors Q6 and Q7, so that base voltage of the transistor Q2 can be set lower while the transistor Q1 is on in order to hold the transistor Q2 to the OFF status. As a result, leak-through current in the transistors Q1 and Q2 can be reduced and switching noises created by said leak-through current can be restrained.

摘要翻译： 为了实现利用所述[驱动电路]的驱动电路和充电泵升压电路，其能够降低在切换期间产生的功耗和噪声。 基于输入到输入端子Tin中的控制信号来控制晶体管Q1和Q2，并且将充电/放电电流输出到输出端子Tout。 具有与晶体管Q1几乎相同的特性的晶体管Q5的基极连接到晶体管Q1的基极，以使晶体管Q5产生对应于晶体管Q1的导通/截止的电流， 并且借助于包括晶体管Q6和Q7的电流镜像电路将来自所述晶体管Q5的电流反射向电阻元件R1，使得晶体管Q2的基极电压可以设定为较低，同时晶体管Q1导通以便保持 晶体管Q2处于关断状态。 结果，可以减小晶体管Q1和Q2中的漏电流，并且可以抑制由所述漏电流产生的开关噪声。

公开(公告)号：EP1069557A3

公开(公告)日：2002-09-11

申请号：EP00304204.1

申请日：2000-05-18

申请人： FUJITSU LIMITED

发明人： Matsuura, Michio, c/o FUJITSU LIMITED

IPC分类号： G11B11/105 ,  H03K17/66

CPC分类号： H03K17/663 ,  G11B5/09 ,  G11B11/10508 ,  G11B11/10534 ,  G11B11/10595

摘要： A drive circuit is provided for a magnetic head that has a bifilar winding with a center tap and is used for a magneto-optical disk drive. A magnetizing control signal MAGCH becomes the high level if there is no magnetic reversal during a period of a predetermined number of clocks and becomes the low level if there is a magnetic reversal. If the magnetizing control signal MAGCH is the low level, a high voltage VH is applied to the center tap of the bifilar winding 31 of the magnetic head via the transistor 39. The transistors 40, 41 or the transistors 42, 43 are turned on in accordance with write data signal DATA, *DATA. Therefore, the magnetizing current flows through one of the winding elements 31a and 31b. If the magnetizing control signal MAGCH is the high level, the transistors 46, 41 or the transistors 48, 43 are turned on in accordance with the write data signal DATA, *DATA. Therefore, the magnetizing current flows from the low voltage VL to both the winding elements 31a and 31b.

公开(公告)号：EP1057263A1

公开(公告)日：2000-12-06

申请号：EP99967393.2

申请日：1999-12-16

申请人： Raytheon Company

发明人： LINDER, Lloyd, F.

IPC分类号： H03K19/003 ,  H03K17/66 ,  G01R31/319 ,  H03K19/018

CPC分类号： H03K19/01837 ,  G01R31/31924 ,  H03K19/00376 ,  H03K19/01806

摘要： An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

公开(公告)号：EP0855704A3

公开(公告)日：2000-08-16

申请号：EP98104433.2

申请日：1992-12-24

申请人： SHARP KABUSHIKI KAISHA

发明人： Ishii, Mitsuo

IPC分类号： G11B11/10 ,  H03K17/66 ,  H03K17/687

CPC分类号： H03K17/661 ,  G11B5/02 ,  G11B11/10508 ,  G11B11/10595 ,  G11B2005/0026 ,  H03K17/6871

摘要： A magnetic head driving device is disclosed. The device includes an inductor for generating a magnetic field, the inductor having a pair of terminals, first auxiliary coil for storing electromagnetic energy, the first auxiliary coil being connected to one of the terminals of the inductor at a first node, second auxiliary coil for storing an electromagnetic energy, the second auxiliary coil being connected to the other terminal of the inductor at a second node, first main switch connected to the first node, second main switch connected to the second node, and control circuit for receiving a first signal indicating generation of a magnetic field by the inductor and a second signal indicating the direction of a magnetic field generated by the inductor and for outputting the second signal for a predetermined period of time in accordance with the first signal to alternately turn on or off the first main switch and the second main switch.

摘要翻译： 一种磁头驱动装置，包括用于产生磁场的电感器（9），所述电感器具有一对端子，用于存储电磁能量的第一辅助线圈（5），所述第一辅助线圈连接到所述第一辅助线圈 在第一节点处的电感器，用于存储电磁能的第二辅助线圈（6），第二辅助线圈在第二节点处连接到电感器的另一个端子，第一主开关（3）连接到第一节点，第二主电路 连接到第二节点的开关（4），以及用于接收指示电感器产生磁场的第一信号的控制电路和指示由电感器产生的磁场方向的第二信号，并输出第二信号 根据第一信号预定的时间段，以交替地打开或关闭第一主开关和第二主开关。