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2021 条记录 (耗时 0.026 秒)

    TERMINAL CONTROL DEVICE
    51.
    发明公开
    TERMINAL CONTROL DEVICE 审中-公开
    终端控制装置

    公开(公告)号：EP3297167A1

    公开(公告)日：2018-03-21

    申请号：EP17188155.0

    申请日：2017-08-28

    申请人： KABUSHIKI KAISHA TOSHIBA ,  Toshiba Infrastructure Systems & Solutions Corporation

    发明人： ARAI, Hideaki

    IPC分类号： H03K19/003

    CPC分类号： H05K7/026 ,  G06F11/2007 ,  G06F2201/85 ,  H03K19/00392

    摘要： According to one embodiment, a terminal control substrate includes a base plate (110, 210, 310, 410, 510) mounted on a terminal device, a first module (112, 212, 312, 412, 512) fixed to the base plate (110, 210, 310, 410, 510), an external connection terminal (113, 213a to 213c, 313, 413a to 413c, 513a to 513c) fixed to the base plate (110, 210, 310, 410, 510) and to which a component comprising a second module being a substitute for the first module (112, 212, 312, 412, 512) is attachable, a controller (111, 211, 311, 411, 511) configured to perform control in the terminal device by using the first module (112, 212, 312, 412, 512) or the second module, and a switching unit (114, 214, 314, 414, 521) configured to switch a connection destination of the controller (111, 211, 311, 411, 511) to any one of the first module (112, 212, 312, 412, 512) and the external connection terminal (113, 213a to 213c, 313, 413a to 413c, 513a to 513c) to which the second module is attached.

    摘要翻译： 根据一个实施例，终端控制基板包括安装在终端设备上的基板（110,210,310,410,510），固定到基板（101）的第一模块（112,212,312,412,512） （110,210,310,410,510），固定到所述基板（110,210,310,410,510）的外部连接端子（113,213a至213c，313,413a至413c，513a至513c）以及 其中包括作为第一模块（112,212,312,412,512）的替代物的第二模块的组件是可附接的，控制器（111,211,311,411,511）被配置为通过以下步骤在终端装置中执行控制： 使用所述第一模块（112,212,312,412,512）或所述第二模块以及切换单元（114,214,314,414,521），所述切换单元被配置为切换所述控制器（111,211,311）的连接目的地 ，411,511）连接到第一模块（112,212,312,412,512）和外部连接端子（113,213a至213c，313,413a至413c，513a至513c）中的任一个，第二模块 被附上。

    INTEGRATED LINEAR CURRENT SENSE CIRCUITRY FOR SEMICONDUCTOR TRANSISTOR DEVICES
    54.
    发明公开
    INTEGRATED LINEAR CURRENT SENSE CIRCUITRY FOR SEMICONDUCTOR TRANSISTOR DEVICES 审中-公开
    半导体晶体管器件的集成线性电流检测电路

    公开(公告)号：EP3244219A1

    公开(公告)日：2017-11-15

    申请号：EP17170829.0

    申请日：2017-05-12

    申请人： Power Integrations, Inc.

    发明人： Mayell, Robert

    IPC分类号： G01R19/00 ,  H03K19/003

    CPC分类号： G01R19/0092 ,  H01L27/0623 ,  H01L29/2003 ,  H01L29/778

    摘要： An integrated circuit (IC) for sensing a current flowing through a transistor device includes a substrate and a current scaling circuit that includes first and second MOSFET devices. The first MOSFET device has a drain coupled to the switched FET at a first node and a source coupled to the substrate. The second MOSFET device has a source coupled to the substrate and a drain coupled to a second node. The first MOSFET device has a channel size that is K times larger than the second MOSFET device. Circuitry is included that equalizes a voltage across both the first MOSFET device and the second MOSFET device.

    摘要翻译： 用于感测流过晶体管器件的电流的集成电路（IC）包括衬底和包括第一和第二MOSFET器件的电流缩放电路。 第一MOSFET器件具有在第一节点处耦合到开关FET的漏极和耦合到衬底的源极。 第二MOSFET器件具有耦合到衬底的源极和耦合到第二节点的漏极。 第一个MOSFET器件的沟道尺寸是第二个MOSFET器件的K倍。 包括的电路均衡第一MOSFET器件和第二MOSFET器件上的电压。

    ELECTRONIC EQUIPMENT AND AUTOMOBILE MOUNTING THE SAME
    56.
    发明授权
    ELECTRONIC EQUIPMENT AND AUTOMOBILE MOUNTING THE SAME 有权
    电子设备和汽车安装相同

    公开(公告)号：EP3048728B1

    公开(公告)日：2017-10-18

    申请号：EP16152176.0

    申请日：2016-01-21

    申请人： Toyota Jidosha Kabushiki Kaisha

    发明人： HIROSE, Satoshi

    IPC分类号： H03K17/567 ,  H03K17/687 ,  H02M3/158 ,  H03K19/003

    CPC分类号： H03K17/168 ,  B60L11/1803 ,  H02M1/32 ,  H02M3/158 ,  H03K17/567 ,  H03K17/6871 ,  H03K19/003

    摘要： An electronic equipment (32) is provided with a semiconductor device (10a) including an electrode joined to an electric conductor via a joint layer (20a), a calculator (58) and a controller. The semiconductor device (10a) is configured to pass current bidirectionally. The calculator (58) is configured to calculate an imbalance electromigration (EM) progression index. The imbalance EM progression index is a difference between a forward current EM progression index and a reverse current EM progression index. The controller (58) is configured to: adopt a condition to speed up an increase rate of the reverse current EM progression index in at least a part of an excessive forward current EM period; and adopt a condition to speed up an increase rate of the forward current EM progression index in at least a part of an excessive reverse current EM period.

    OVERVOLTAGE PROTECTION DEVICE
    57.
    发明公开
    OVERVOLTAGE PROTECTION DEVICE 审中-公开
    过电压保护装置

    公开(公告)号：EP3193450A3

    公开(公告)日：2017-10-04

    申请号：EP16206339.0

    申请日：2016-12-22

    申请人： Alpine Electronics, Inc.

    发明人： Tanaka, Norihiko

    IPC分类号： H03K19/003 ,  H01L27/02

    CPC分类号： H02H9/044 ,  H01L27/0647 ,  H01L29/866 ,  H02H1/0007 ,  H02H1/0061 ,  H03K19/00315

    摘要： An "overvoltage protection device" that protects a device from an overvoltage of a signal line regardless of an ON/OFF state of a power supply is provided.
    A resistor (R) that is connected in series between an internal signal line (SL) connected to a communication terminal (122) of a processor (12) and a communication line (CL), a diode (D) of which a cathode is connected to the internal signal line (SL) and an anode is connected to a ground (GND), and a PNP transistor (Q) of which a base is connected to a power supply terminal (121), an emitter is connected to the internal signal line (SL), and a collector is connected to the ground (GND) are provided. When a base-emitter voltage (a junction saturation voltage) of the transistor (Q) in operation is defined as V BE and a power source (VDD) is turned on (a voltage V1) by the operation of the transistor (Q), a voltage of the internal signal line (SL) is limited to the source voltage VDD + V BE (a). When the power source (VDD) is turned off (a voltage 0 V), the voltage of the internal signal line (SL) is limited to the source voltage 0 V + V BE (b).

    摘要翻译： 提供一种“过电压保护装置”，其保护装置免受信号线的过电压的影响，而不管电源的开/关状态如何。 在与处理器（12）的通信端子（122）连接的内部信号线路（SL）与通信线路（CL）之间串联连接电阻（R），阴极为 连接到内部信号线（SL）并且阳极连接到地（GND），并且PNP晶体管（Q）的基极连接到电源端子（121），发射极连接到内部信号线 信号线（SL），并且集电极连接到地（GND）。 当通过晶体管（Q）的操作将晶体管（Q）工作时的基极 - 发射极电压（结饱和电压）定义为VBE且电源（VDD）导通（电压V1）时， 内部信号线（SL）的电压被限制为源电压VDD + VBE（a）。 当电源（VDD）关闭时（电压为0 V），内部信号线（SL）的电压被限制在源电压0 V + VBE（b）。

    INTEGRATED DEVICE FOR IMPLEMENTING A PHYSICAL UNCLONABLE FUNCTION AND A PHYSICAL UNCLONABLE CONSTANT
    60.
    发明公开
    INTEGRATED DEVICE FOR IMPLEMENTING A PHYSICAL UNCLONABLE FUNCTION AND A PHYSICAL UNCLONABLE CONSTANT 审中-公开
    用于实现物理无作用函数和物理不可变常量的集成设备

    公开(公告)号：EP3202041A1

    公开(公告)日：2017-08-09

    申请号：EP15791746.9

    申请日：2015-10-01

    申请人： Universita' Degli Studi di Udine

    发明人： BERNARDINI, Riccardo ,  RINALDO, Roberto

    IPC分类号： H03K19/003 ,  H04L9/32

    CPC分类号： H03K19/003 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/12

    摘要： A PUC (Physical Unclonable Constant) cell characterized by a very low complexity comparable to that of an SRAM cell and by much greater reliability than an SRAM cell as it is characterized by only one stable equilibrium point the position of which depends on random differences introduced during the step of manufacturing the chip. The PUC cell according to the present invention is also stable over a wide range of operating temperatures and offers considerable noise immunity, thus making the use of stabilizers adapted to ensure the correct output and which are normally used along with conventional SRAM type cells unnecessary.

    摘要翻译： PUC（Physical Unclonable Constant，物理不可复制常数）单元的特点是复杂性非常低，与SRAM单元的复杂度相当，并且比SRAM单元具有更高的可靠性，因为它的特点是只有一个稳定的平衡点，其位置取决于随机差异 制造芯片的步骤。 根据本发明的PUC单元在很宽的工作温度范围内也是稳定的，并且具有相当的抗噪声性能，从而使得使用适于确保正确输出的稳定器并且通常与传统的SRAM型单元一起使用是不必要的。