公开(公告)号：EP0583371B1

公开(公告)日：2000-10-18

申请号：EP92911860.2

申请日：1992-04-29

申请人： LATTICE SEMICONDUCTOR CORPORATION

发明人： SHEN, Ju ,  CHAN, Albert, L. ,  SHANKAR, Kapil ,  TSUI, Cyrus

IPC分类号： H03K19/177 ,  H03K19/21 ,  H03K19/173

CPC分类号： H03K19/1736

公开(公告)号：EP1041720A1

公开(公告)日：2000-10-04

申请号：EP00302108.6

申请日：2000-03-15

申请人： FUJITSU LIMITED

发明人： Tatsuoka, Masato, c/o Fujitsu Limited

IPC分类号： H03K19/21 ,  G06F7/00

CPC分类号： G06F9/30032 ,  G06F7/02

摘要： A zero determination signal generating circuit which generates a zero determination signal for determining whether or not the output data of a shifter is zero is provided. With the zero determination signal generating circuit of the present invention, high-speed zero determination can be achieved. More specifically, in a case where the shifter functions as a left shifter, as a shifting operation of a left shifter unit (including a plurality of left shifters) is performed, predetermined bits in the outputs of left shifters having a shift amount of 0 are subjected to an OR operation or buffered so as to generate a zero determination signal. In a case where the shifter functions as a right shifter, as a shifting operation of a right shifter unit (including a plurality of right shifters) is performed, predetermined bits in the outputs of right shifters having a shift amount of 0 are subjected to an OR operation or buffered so as to generate a zero determination signal.

摘要翻译： 提供了一种零判定信号发生电路，其生成用于确定移位器的输出数据是否为零的零确定信号。 利用本发明的零判定信号发生电路，可以实现高速零位确定。 更具体地说，在移位器用作左移位器的情况下，作为左移位器单元（包括多个左移位器）的移位操作，执行移位量为0的左移位器的输出中的预定位是 经受或操作或缓冲以产生零确定信号。 在移位器用作右移位器的情况下，作为右移位器单元（包括多个右移位器）的移位操作，执行移位量为0的右移位器的输出中的预定位， 或操作或缓冲以产生零确定信号。

公开(公告)号：EP0661814B1

公开(公告)日：1999-03-31

申请号：EP93830526.5

申请日：1993-12-28

申请人： STMicroelectronics S.r.l.

发明人： Olivo, Marco ,  Maccarrone, Marco

IPC分类号： H03K21/38 ,  H03K19/21 ,  G11C16/06

CPC分类号： H03K21/38

公开(公告)号：EP0570597A1

公开(公告)日：1993-11-24

申请号：EP92924898.7

申请日：1992-12-09

申请人： FUJITSU LIMITED

发明人： AKAOGI, Takao Fujitsu Limited 1015, Kamikodanaka ,  KAWASHIMA, Hiromi Fujitsu Limited ,  TAKEGUCHI, Tetsuji Fujitsu Limited ,  HAGIWARA, Ryoji Fujitsu Limited ,  KASA, Yasushi Fujitsu Limited 1015, Kamikodanaka ,  ITANO, Kiyoshi Fujitsu Limited 1015, Kamikodanaka ,  OGAWA, Yasushige Fujitsu VLSI Limited ,  KAWAMURA, Shouichi Fujitsu Limited

IPC分类号： G11C16/06 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

摘要： A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.

摘要翻译： 闪存通过缩短擦除时间来改善其擦除操作，其中当通过同时选择字线和位线中的至少一个的数行时，在擦除之前写入数据时，将数据写入多个晶体管 同意。

公开(公告)号：EP0238091A3

公开(公告)日：1989-12-27

申请号：EP87104102.6

申请日：1987-03-20

申请人： FUJITSU LIMITED

发明人： Suzuki, Atsushi ,  Nagashima, Masashi

IPC分类号： H03K19/21 ,  G06F11/10

CPC分类号： H03K19/215

摘要： A multiple-input logic circuit for earrying out an even parity check operation or an odd parity check operation on a plurality of input signals has such a circuit construction that a signal only passes through a maximum of essentially two gates between an input and an output of the multiple-input logic circuit, so as to increase the operation speed and reduce the number of elements constituting the multiple-input logic circuit.

摘要翻译： 用于对多个输入信号执行偶校验操作或奇校验操作的多输入逻辑电路具有这样一种电路结构：信号仅通过输入和输出之间的基本上两个门极大 多输入逻辑电路，从而增加操作速度并减少构成多输入逻辑电路的元件的数量。

公开(公告)号：EP0322885A3

公开(公告)日：1989-08-30

申请号：EP88121781.4

申请日：1988-12-28

申请人： KABUSHIKI KAISHA TOSHIBA ,  Toshiba Micro-Computer Engineering Corporation

发明人： Tago, Nobuo

IPC分类号： H03K19/21 ,  G06F7/02

CPC分类号： H03K19/215 ,  G06F7/02

摘要： A coincidence determination circuit capable of reducing number of elements by providing a time period during which the coincidence determination is enabled. This coincidence determination circuit comprises, a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor (T3-T6) having a gate to which a clock signal is inputted, a second P-channel transistor (T11-T14) having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor (T19-T22) having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third P-channel transistors being connected in series, respective outputs of the first bit comparison units being wired-OR connected to a first output line (N1), said first output line serving to pull its signal level down in response to the clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-­channel transistor (T7-T10) having a gate to which an inverted signal of the clock signal (CLK) is inputted, a second N-channel transistor (T15-T18) having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor (T23-­T26) having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third N-channel transistors being connected in series, respective outputs of the second bit comparison units being wired-OR connected to a second output line (N2), the second output line serving to pull its level up by the inverted signal of the clock signal; and an output unit (2, 3) for producing a coincidence output when the first output line is at a low level and the second output line is at a high level.

公开(公告)号：EP0246351B1

公开(公告)日：1988-12-07

申请号：EP86107040.7

申请日：1986-05-23

申请人： Deutsche ITT Industries GmbH

发明人： Woods, Brian

IPC分类号： H03K5/26 ,  H03K19/21

CPC分类号： H03K5/26

公开(公告)号：EP0238091A2

公开(公告)日：1987-09-23

申请号：EP87104102.6

申请日：1987-03-20

申请人： FUJITSU LIMITED

发明人： Suzuki, Atsushi ,  Nagashima, Masashi

IPC分类号： H03K19/21 ,  G06F11/10

CPC分类号： H03K19/215

摘要： A multiple-input logic circuit for earrying out an even parity check operation or an odd parity check operation on a plurality of input signals has such a circuit construction that a signal only passes through a maximum of essentially two gates between an input and an output of the multiple-input logic circuit, so as to increase the operation speed and reduce the number of elements constituting the multiple-input logic circuit.

公开(公告)号：EP0222648A1

公开(公告)日：1987-05-20

申请号：EP86402287.6

申请日：1986-10-14

申请人： THOMSON-CSF

发明人： Pham, Ngu Tung

IPC分类号： H03K19/094 ,  H03K19/21 ,  H03K23/66 ,  H03K23/40

CPC分类号： H03K19/0952 ,  H03K19/217 ,  H03K23/40 ,  H03K23/667

摘要： L'invention concerne la logique rapide programmable.
La porte logique selon l'invention comprend deux inverseurs montés en parallèle, constitués par un transistor (1, 3) et une charge saturable (2, 4).Le second inverseur (3+4) est alimenté à travers un transistor (6) dont la grille, reliée au drain, est réunie au drain (7) du premier inverseur (1+2), qui peut avoir des entrées supplémentaires (1,9) (fonction OU). Un triplet de trois portes logiques montées en série (11, 12, 13) comprend une entrée de programmation (C₁) sur la troisième porte (13), une sortie de rebouclage et, dans le cas d'une séquence de triplets, des entrées de rebouclage sur la première porte (11) du premier triplet (11, 12, 13). Un circuit logique programmable est obtenu par une séquence de triplets montés en série, tous rebouclés sur la première porte (11) de la séquence. La programmation est obtenue en mettant une ou deux entrées de programmation au niveau 0 logique.
Application aux circuits diviseurs de fréquence program­mables, dont les rapports se suivent un par un.

公开(公告)号：EP0187584A1

公开(公告)日：1986-07-16

申请号：EP85402456.9

申请日：1985-12-10

申请人： THOMSON-CSF

发明人： Pham, Ngu Tung

IPC分类号： H03K19/21

CPC分类号： H03K19/217

摘要： e L'invention concerne une porte à coïncidence, dont la sortie ne change d'état que si les entrées sont de même niveau logique.
Elle comporte deux inverseurs montés en parallèle, constitués chacun par un transistor (21, 22) dont la source est à la masse (10) et le drain alimenté par une résistance (23, 24), les grilles (11, 12) constituant les entrées de la porte. Ses caractéristiques sont que les deux résistances (23, 24) sont des résistances saturables, identiques, et que le premier inverseur (21 + 23) est alimenté à partir d'une tension fixe (16) tandis que le second inverseur (22+24) est alimenté,à travers une diode Schottky (25) montée dans le sens passant, à partir du point (13) commun à la première résistance saturable (23) et au drain du premier transistor (21). Le point (15) commun à la diode Schottky (25) et à la seconde résistance saturable (24) constitue la sortie de la porte à coïncidence.
Application aux circuits logiques séquentiels.