公开(公告)号：EP3531289B1

公开(公告)日：2020-11-04

申请号：EP19156613.2

申请日：2019-02-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Mr. Roberto ,  RANJAN, Mr. Om

IPC: G06F11/10

公开(公告)号：EP3719636A1

公开(公告)日：2020-10-07

申请号：EP20162502.7

申请日：2020-03-11

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Roberto

IPC: G06F8/65 ,  G06F11/27 ,  G07C5/00 ,  G06F21/64

Abstract: A processing system (10a) is described. The processing system comprises a digital processing unit and a non-volatile memory (104) configured to store a firmware for the digital processing unit. A diagnostic circuit (118) is configured to execute self-test operations of the processing system (10a) in response to a diagnostic mode enable signal (DEN). A reset circuit (116) is configured to perform a complex reset of the processing system (10a) by:
- in response to a given event, generating a first reset, wherein the processing system (10a) is configured (1084) to set the diagnostic mode enable signal (DEN) in response to the first reset, thereby activating the executing of the self-test operations, and
- once the self-test operations have been executed, generating a second reset.
Moreover, the non-volatile memory (104) comprises a first and a second programmable memory area for storing a first and a second updateable firmware image, and a third memory area for storing signature data (OTA_SIG), wherein the processing system (10a) executes the first or second firmware image as a function of a firmware selection signal (FW_SEL) determined by a signature search circuit (1086) as a function of the signature data (OTA_SIG). In particular, the signature search circuit (1086) is configured to:
- in response to the first reset, read the signature data (OTA_SIG), and
- in response to the second reset, generate the firmware selection signal (FW SEL) as a function of the signature data (OTA_SIG) read in response to the first reset.

公开(公告)号：EP3514685B1

公开(公告)日：2020-10-07

申请号：EP19150934.8

申请日：2019-01-09

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F9/445 ,  G06F9/4401

公开(公告)号：EP3661056A1

公开(公告)日：2020-06-03

申请号：EP19209093.4

申请日：2019-11-14

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO,Roberto

IPC: H03K5/19 ,  G06F11/30 ,  H03K19/007

Abstract: A processing system (10a) is described. The processing system (10a) comprises a timer circuit (122) and a processing circuit (110). The timer circuit (122) generates, in response to a clock signal ( CLK ), a system time signal ( GST ) comprising a plurality of bits indicative of a time tick-count. The processing circuit (110) receives the system time signal ( GST ), detects (1102) whether the system time signal ( GST ) reaches or exceeds a given reference value, and starts execution of a given processing operation in response to the detection.
Specifically, the timer circuit (122) has associated an error code calculation circuit (1230) configured to compute a first set of error detection bits ( EDB ) as a function of the bits of the system time signal (GST). The processing circuit (110) has associated an error detection circuit (1112). The error detection circuit (1112) computes a second set of error detection bits as a function of the bits of said system time signal ( GST ) received, compares the first set of error detection bits ( EDB ) with the second set of error detection bits, and generates an error signal ( ERR2 ) in response to the comparison.

公开(公告)号：EP2447872B1

公开(公告)日：2020-03-11

申请号：EP10306177.6

申请日：2010-10-27

Applicant: ST Microelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： Degauque, Laurent ,  Böhler, Jürgen ,  Charles, Alexandre ,  Rizzo, Pierre

IPC: G06K7/10

公开(公告)号：EP3531289A1

公开(公告)日：2019-08-28

申请号：EP19156613.2

申请日：2019-02-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Mr. Roberto ,  RANJAN, Mr. Om

IPC: G06F11/10

Abstract: A processing system (10a) is described. The processing system (10a) comprises configuration data clients (112), wherein with each configuration data client (112) is associated a respective address (ADR). The configuration data (CD) for the plurality of configuration data clients (112) are store in a non-volatile memory (104), wherein the configuration data (CD) are stored in the form of data packets (DCF_x, DCF_y, DCF_z) comprising an attribute field identifying the address (ADR) of one of the configuration data clients (112) and the respective configuration data. A hardware configuration module (108) sequentially reads (1080) the data packets from the non-volatile memory (104) and transmit the configuration data (DATA) read to the respective configuration data client (112).
Specifically, the non-volatile memory (104) comprises first signature data (HASH), wherein the hardware configuration module (108) reads also the first signature data (HASH). Moreover, the processing system (10a) comprises a signature calculation circuit (130) configured to calculate second signature data (HASH') as a function of the respective configuration data (DATA) transmitted to the configuration data clients (112) and/or stored in the configuration data clients (112). Accordingly, a signature verification circuit (132) may compare the first signature data (HASH) with the second signature data (HASH') and possibly generate an error signal (ERR).

公开(公告)号：EP3514685A1

公开(公告)日：2019-07-24

申请号：EP19150934.8

申请日：2019-01-09

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F9/445

Abstract: The present disclosure relates to a processing system. The processing system comprises a plurality of configuration data clients (112), wherein each configuration data client (112) is configured to receive configuration data (CD) addressed to a respective address and store the configuration data (CD) received in a respective register (118). The processing system comprises also at least one hardware block configured to change operation as a function of the configuration data (CD) stored in the registers (118) of the configuration data clients (112), and a non-volatile memory (104) configured to store the configuration data (CD) for the plurality of configuration data clients (112). Specifically, the configuration data are stored in the form of data packets. A hardware configuration module (108) sequentially reads the data packets from the non-volatile memory (104) and transmit the respective configuration data read from the non-volatile memory (104) to the respective configuration data client (112).
Specifically, at least one of the configuration data clients (112) is configured to receive a first set of configuration data addressed to the respective address and store (1024) the first set of configuration data received in the respective register (118). Moreover, the configuration data client (112) may receive a second set of configuration data addressed to the respective address. In response to the second set of configuration data, the configuration data client (112) verifies (1022) whether further configuration data may be written to the respective register as a function of at least one type identification signal (TI).

公开(公告)号：EP3401826A3

公开(公告)日：2019-02-13

申请号：EP18171148.2

申请日：2018-05-08

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  GROSSIER, Nicolas Bernard ,  DI SIRIO, Giovanni ,  RE FIORENTIN, Lorenzo

IPC: G06F21/57 ,  G06F21/60 ,  G06F21/77 ,  H03K19/177

Abstract: A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.

公开(公告)号：EP3413194A1

公开(公告)日：2018-12-12

申请号：EP18173913.7

申请日：2018-05-23

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Roberto

IPC: G06F9/445

CPC classification number: G06F3/0679 ,  G05B19/056 ,  G06F12/0246 ,  G06F13/38 ,  G06F21/76

Abstract: A processing system is described. The processing system comprises a processing unit (102), and at least one hardware block (110) configured to change operation as a function of life cycle data (LCD). Specifically, a one-time programmable memory (104; 126) comprises original life cycle data (OLCD) and a hardware configuration module (108) reads the original life cycle data (OLCD) from the one-time programmable memory (104; 126) and provides the original life cycle data (OLCD) to the at least one hardware block (110).
Specifically, the hardware configuration module (108) comprises a register providing the life cycle data (LCD) to the at least one hardware block (110) . The hardware configuration module (108) is configured to:
- store the original life cycle data (OLCD) in the register, thereby providing the original life cycle data to the at least one hardware block (110); and
- receive a command (CMD) from the processing unit (102), wherein the command (CMD) comprising a write request for storing new life cycle data in the register, thereby providing the new life cycle data to the at least one hardware block (110).

公开(公告)号：EP3401183A1

公开(公告)日：2018-11-14

申请号：EP18171268.8

申请日：2018-05-08

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  GROSSIER, Nicolas Bernard ,  VITTIMANI, Roberta

IPC: B60W50/04 ,  G06F11/14

Abstract: A processing system (10a) is described. The processing system (10a) comprises at least one hardware block configured to change operation as a function of configuration data (CD), a non-volatile memory (104) comprising the configuration data (CD) for the at least one hardware block, and configuration means (108, 112) configured to read the configuration data (CD) from the non-volatile memory (104) and provide the configuration data (CD) read from the non-volatile memory (104) to the at least one hardware block.
The configuration means (108, 112) are configured to:
- receive mode configuration data (MDU);
- read the configuration data (CD) from the non-volatile memory (104);
- test whether the configuration data (CD) contain errors by verifying whether the configuration data (CD) are corrupted and/or invalid;
- in case the configuration data (CD) do not contain errors, activating a normal operation mode of the processing system (10a) by providing the configuration data (CD) read from the non-volatile memory (104) to the at least one hardware block (110); and
- in case the configuration data (CD) do contain errors, activating an error operation mode of the processing system (10a) as a function of the mode configuration data (MDU) by:
- providing reset values (120) to the at least one hardware block (110) when the mode configuration data (MDU) indicate that a reset mode should be activated; and
- providing preset configuration data (122) to the at least one hardware block (110) when the mode configuration data (MDU) indicate that a degraded mode should be activated.