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公开(公告)号：EP0096163A3
公开(公告)日：1984-10-17
申请号：EP83102173
申请日：1983-03-05
发明人： Inagawa, Jun , Nagumo, Masahide , Kojima, Tadashi
CPC分类号： H03M13/15 , G06F7/726 , G11B20/1809
摘要： An apparatus divides one element a' of a Galois field GF(2 m ) by another element α i of the field. Divider data α i are supplied to one of the first linear shift registers (A, to A4) and to the other first linear shift registers through α N1 , α N2 ,... multiplier circuits (51 to 53), respectively. Simultaneously, dividend data α i are supplied to one of the second linear shift registers (B, to B 4 ) and to the other second linear shift registers through α N1 , α N2 , ... multiplier circuits (58 to 60), respectively. "1" detector circuits (55 to 57) are connected to the outputs of the first linear shift registers (A, to A 4 ), respectively. The first linear shift registers (A, to A4) and the second linear shift registers (B 1 to B 4 ) are shifted several times until any "1" detector circuit (55 to 57) detects "1' in response to output signals from a 2-input AND gate (AND,,). When "1" is detected, a NOR gate (NOR, o ) supplies a signal of logical "0" to the AND gate (AND,,), whereby the AND gate (AND 11 ) stops supplying output signals. 2-input AND circuits (61 to 64) are connected at one input terminal to the outputs of the "1" detector circuits (54 to 57) and at the other input terminal to the outputs of the second linear shift registers (B, to B 4 ). The AND circuit connected to the "1" detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division α i - a i , are delivered through an OR circuit (65).
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公开(公告)号：EP0029226B1
公开(公告)日：1984-07-25
申请号：EP80107015.2
申请日：1980-11-13
IPC分类号： G11B5/09
CPC分类号： G11B20/1809
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公开(公告)号：EP0096106A1
公开(公告)日：1983-12-21
申请号：EP82109205.3
申请日：1982-10-05
CPC分类号： G11B20/1403 , G11B20/10527
摘要： A phase locked loop (PLL) control circuit for a digital audio disk system is disclosed which has a voltage-controlled oscillator (VCO) (116), a reference signal generator (106) for generating a reference signal corresponding to the phase state of a digital audio signal when the digital audio signal is reproduced or read out and which is recorded on a digital audio disk (DAD) (54) to have a maximum or minimum inverting period value predetermined by the eight to fourteen modulation (EFM) method, a phase comparator (110) connected to the output terminal of the reference signal generator (106) and the VCO (116), a detector (122) for detecting the maximum inverting period value included in the digital audio signal; and an adder (112) for adding outputs from the phase comparator (110) and the detector (122) and for supplying a sum result as an oscillation control signal to the VCO (116).
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公开(公告)号：EP0056140A3
公开(公告)日：1983-02-02
申请号：EP81110607
申请日：1981-12-18
发明人： Kojima, Tadashi , Todokoro, Shigeru
IPC分类号： G11B05/86
CPC分类号： G11B15/125 , G11B5/86 , G11B27/032 , G11B27/36
摘要： A signal copy device for a digital record/reproduction system includes an encoding circuit (12) for producing a first digital encoded signal corresponding to an analog audio signal. The encoding circuit (12) is connected to a first VTR (24) through a switch section (16) of a switch circuit (18) and : a first digital signal processor (22). A second VTR (64) reproduces and generates a digital encoded audio signal to be copied. The switch circuit (18) is connected to the encoding circuit (12) and the second VTR (64). The switch circuit (18) includes two switch sections (16, 28) which operate in cooperation with each other. When a reproduction signal is generated from the second VTR (64), the two switch sections (16, 28) are switched. The reproduction signal is supplied to the first VTR (24) through these switch sections (16, 28), thus accomplishing copying.
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公开(公告)号：EP0056128A3
公开(公告)日：1983-01-12
申请号：EP81110507
申请日：1981-12-16
发明人： Nagumo, Masahide , Kojima, Tadashi
CPC分类号： H03L7/1974 , H03L7/08 , H03L7/087
摘要： A phase synchronizing circuit has a phase locked loop including a first phase comparison circuit (13) to which a predetermined input signal is supplied, a voltage controlled oscillator (VCO) (15) for producing an oscillation output the frequency of which is controlled by the output of the first phase comparison circuit, and first frequency dividing means (16, 17, 18) having at least a first frequency divider (16) to divide the output of VCO. The phase synchronizing circuit further includes second frequency dividing means (19, 20) for dividing the output frequency of VCO, a second phase comparison circuit (21) for comparing the phase of a first clock signal (f a ') which is led from first dividing means, with that of a second clock signal (f a ) which is led from second dividing means, and a controlling means for controlling the first frequency divider and second phase comparison circuit so as to synchronize phases of first and second clock signals. The controlling means controls the frequency dividing ratio of first frequency dividing circuit according to the phase difference between first and second clock signals in such a way that the frequency dividing ratio becomes 1/N, 1/(N+1) and 1/{[N+(N+1)]/2} wherein N is a positive integer. Phases of first and second clock signals can be synchronized accurately.
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公开(公告)号：EP0047955A3
公开(公告)日：1982-10-13
申请号：EP81107028
申请日：1981-09-07
发明人： Todokoro, Shigeru , Kojima, Tadashi
摘要： A wave-shaping circuit which comprises a comparator (12) for comparing the level of a signal reproduced from a magnetic tape on which, for example, PCM signals are recorded with the level of a reference signal, and a D flip-flop circuit (26) for holding an output signal from the comparator for a prescribed period. Where the reproduced signal has a higher level than the original level of the reference signal, then the reference signal is made to have a higher level than the original level by an output signal from the D flip-flop circuit (26), that is, an output signal from the comparator (12). Where the reproduced signal has a lower level than the original level of a reference signal, then the reference signal is made to have a lower level than the original level by the output signal from the comparator (12). As a result, strains occurring at the high density recording are not reproduced.
摘要翻译： 波形整形电路包括比较器（12）和D触发器电路（12），比较器（12）用于将从记录有例如PCM信号的磁带再现的信号的电平与参考信号的电平进行比较， 26），用于在规定的时间内保持来自比较器的输出信号。 在再现信号具有比参考信号的原始电平高的电平的情况下，通过来自D触发器电路（26）的输出信号使参考信号具有比原始电平更高的电平，即， 来自比较器（12）的输出信号。 在再现信号具有比参考信号的原始电平低的电平的情况下，通过来自比较器（12）的输出信号使参考信号具有比原始电平更低的电平。 结果，在高密度记录下出现的应变不被再现。
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公开(公告)号：EP0052520A3
公开(公告)日：1982-06-30
申请号：EP81305444
申请日：1981-11-18
发明人： Hoshimi, Susumo , Kojima, Tadashi
CPC分类号： G11B5/09 , G11B27/032 , G11B27/323 , G11B2220/90
摘要： A PCM signal processor having a signal input terminal which receives a PCM data signal from a PCM data signal reproducing apparatus such as a VTR (18R), a memory (14) for storing the PCM data signal, a standardized signal input terminal for providing a standardized signal corresponding to a synchronizing signal for synchronizing the VTR (18P), an address counter (38) for designating the address of the memory (14) which is to be read, and means for providing the address counter (38) with preset data in response to the standardized signal.
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公开(公告)号：EP0052519A3
公开(公告)日：1982-06-23
申请号：EP81305443
申请日：1981-11-18
发明人： Hoshimi, Susumu , Kojima, Tadashi
CPC分类号： G11B5/86 , G11B27/032 , G11B2220/90 , G11B2220/913
摘要： A pulse code modulation (PCM) signal recording system includes a first signal processor (1 to 7) for processing a recording signal into a predetermined PCM signal, a second signal processor (18 to 24) for processing a reproduced PCM signal into a recording signal, a first clock signal generator (9) generating a master clock signal, a second clock signal generator (12 to 14) generating at least one recording clock signal from the master clock signal, the recording clock signal being supplied to the first signal processor (1 to 7), a third clock signal generator (27) generating at least one reproducing clock signal from the master clock signal, the reproducing clock signal being supplied to the second signal processor (18 to 24), a comparator (32) digitally comparing the phases of the second and third clock signals and producing a control signal, and a controller (29) receiving the control signal and controlling the second or third clock signal so that they are synchronized.
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69.发明公开
公开(公告)号：EP0053505A2
公开(公告)日：1982-06-09
申请号：EP81305641.3
申请日：1981-11-27
发明人： Hoshimi, Susumu , Kojima, Tadashi
CPC分类号： G11B20/1809
摘要： A PCM signal processing apparatus is arranged to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words. The apparatus has an error detector (16) responsive to the error detection words for detecting errors in a received transmission block and error identifying means (18, 22, 23) for identifying errors in each of the time-interleaved words included in the received transmission block which has been detected. A de-interleaver (17) is provided for time-deinterleaving each received transmission block to recover a de-interleaved block comprising de-interleaved PCM and error correction words, with errors in the de-interleaved words being respectively identified. A syndrome generating device (18) is coupled to the de-interleaver (17) for generating error syndromes using the de-interleaved PCM and error correction words in the de-interleaved block. An error correcting device (20) responsive to the error syndromes corrects erroneous PCM words in the de-interleaved block as a function of the remaining error free PCM and the error correction words in the de-interleaved block. An error compensating device (21) is responsive to the identification of errors by the error identifying device and compensates the erroneous PCM words in the de-interleaved block with a substitute PCM word when error correction by the error correcting device (20) is impossible. An inhibit device (24) inhibits the error correcting device (20) when all of the error detection words in the de-interleaved block are identified as erroneous and it discontinues inhibiting when the relationship between the identification by the error identifying device and the error syndrome indicates that no error exists.
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