公开(公告)号：EP1242868A1

公开(公告)日：2002-09-25

申请号：EP00957863.4

申请日：2000-08-25

Applicant: LEXAR MEDIA, INC.

Inventor： ESTAKHRI, Petro ,  IMAN, Berhanu

IPC: G06F9/00 ,  G06F12/06 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102

Abstract: An embodiment of the present invention includes a nonvolatile memory system for storing sector information in storage locations (232) within nonvolatile memory (16) organized into blocks, a plurality of blocks defining a super block and each block having a predetermined plurality of sectors. The nonvolatile memory system includes a controller (14) for shifting sector information to a first (210) and a second block (216) of a particular super block (204) and writing sector information to the first block (210) of the particular super block, wherein shifting to the second block (216) occurs entirely during the writing to the first block thereby decreasing the time required to perform write operations to blocks and increasing overall system performance.

公开(公告)号：EP1239490A2

公开(公告)日：2002-09-11

申请号：EP02010893.2

申请日：1996-10-03

Applicant: Agate Semiconductor, Inc.

Inventor： Khan, Sakhawat M.

IPC: G11C11/56

CPC classification number: G11C8/12 ,  G11C8/04 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C19/00 ,  G11C29/00 ,  G11C2211/5624 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds to the multiple bits. The cells are organised into blocks each with reference and data memory cells. Reference voltage levels (REFA0-REFA15, REFB0-REFB15) are generated so programming circuits can simultaneously set voltages in the data memory cells corresponding to data bits with respect to a first set of reference voltage levels. Reading circuits compare the voltages set in the data memory cells with respect to a second set of reference voltage levels programmed in the reference memory cells to determine the data bits.

Abstract translation: 每个存储单元存储多个位的集成电路进行说明。 存储在存储器单元中的电荷的量对应于多个位。 将细胞组织成与参考和数据的存储器单元的每个块。 参考电压电平（REFA0-REFA15，REFB0-REFB15）作为编程电路可在数据存储单元对应于数据比特相对于第一组的参考电压电平同时设定电压被生成。 读取电路比较电压在数据存储单元相对于设定为第二组中的基准存储单元编程为确定性的矿井中的数据位的参考电压电平。

公开(公告)号：EP1116236B1

公开(公告)日：2002-05-15

申请号：EP99942182.9

申请日：1999-08-16

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： KUO, Tiao-Hua ,  KASA, Yasushi ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

IPC: G11C5/00 ,  G11C8/00 ,  G11C16/06

CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08

Abstract: A method of forming flexibly partitioned metal line segments (10 and 12) for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer (2) comprising a plurality of basic metal layer segments (2a, 2b, 2c, ...2j) separated by a plurality of gaps (6a, 6b, 6c, ...6i), each of the gaps having a predefined gap interval length, and providing a metal option layer (8) comprising a plurality of metal option layer segments on the basic metal layer (2), the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.

公开(公告)号：EP0549139B1

公开(公告)日：2002-03-06

申请号：EP92310797.3

申请日：1992-11-25

Applicant: SUN MICROSYSTEMS, INC. ,  XEROX CORPORATION

Inventor： Chesley, Gilman ,  Gastinel, Jean A. ,  Cerauskis, Fred

IPC: G06F13/42 ,  G11C7/00

CPC classification number: G11C8/12 ,  G06F13/4243 ,  G11C7/22

公开(公告)号：EP0759618B1

公开(公告)日：2001-11-14

申请号：EP96112536.6

申请日：1996-08-02

Applicant: NEC CORPORATION

Inventor： Saeki, Takanori, c/o NEC Corp.

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/12

公开(公告)号：EP0829086B1

公开(公告)日：2001-10-24

申请号：EP95923687.8

申请日：1995-05-31

Applicant: Macronix International Co., Ltd.

Inventor： LIOU, Kong-Mou ,  YIU, Tom, Dang-Hsing ,  WAN, Ray-Lin ,  CHENG, Yao-Wu ,  HUNG, Chun-Hsiung ,  LIN, Tien-Ler ,  HU, Ting-Chung

IPC: G11C7/00 ,  G11C29/00 ,  G06F11/00

CPC classification number: G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated memory array having a plurality of sectors (10) selected by an address decoder (11, 13) in response to an N bit field in an address (17). If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder (12) to prevent access to the defective sectors while maintaining sequential addressing remaining in the array. The step of partitioning includes configuring the sector decoder (12) to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the address bits in common with the defective sector when m is between 1 and N-1.

公开(公告)号：EP0823117B1

公开(公告)日：2001-09-26

申请号：EP96913137.4

申请日：1996-04-25

Applicant: INTEL CORPORATION

Inventor： BALTAR, Robert, L. ,  BAUER, Mark, E. ,  FRARY, Kevin, W. ,  PUDAR, Steven, D. ,  SWEHA, Sherif, R.

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A nonvolatile memory (31) includes a global line (65) and a first block (61) and a second block (62). The first block includes a plurality of first local lines (71) and a first decoder (78) coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines (81) and a second decoder (88) coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with an address when the second decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that the interference between the first and second blocks is eliminated during memory operation.

公开(公告)号：EP1113449A1

公开(公告)日：2001-07-04

申请号：EP00125984.5

申请日：2000-11-28

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Fujino, Takeshi, Mitsubishi Denki Kabushiki Kaisha ,  Inoue, Kazunari, Mitsubishi Denki Kabushiki Kaisha ,  Yamazaki, Akira, Mitsubishi Denki Kabushiki Kaisha ,  Arimoto, Kazutami, Mitsubishi Denki Kabushiki K.

IPC: G11C11/408 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C8/18 ,  G11C11/4087

Abstract: A central row-related control circuit (1) transmits an internal row address signal (RA )to each memory sub block in banks of memory mats (MM1, MM2) asynchronously with an external clock signal, and latches a block selection signal (BS )for specifying a memory sub block synchronously with an internal dock signal (CLKR) for one dock cycle period for transmission to each memory sub block (MSB). A spare determination circuit (4) performs spare determination asynchronously with the dock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

Abstract translation: 中央行相关控制电路（1）与外部时钟信号异步地将内部行地址信号（RA <8：0>）发送到存储器存储体组（MM1，MM2）中的每个存储器子块，并锁存块 选择信号（BS <7：0>），用于与用于发送到每个存储器子块（MSB）的一个停放周期周期的内部停靠信号（CLKR）同步地指定存储器子块。 备用确定电路（4）与停靠信号异步地执行备用确定。 可以提供容易适应银行扩张而不增加芯片面积并能够实现高速存取的半导体存储器件。

公开(公告)号：EP1105877A2

公开(公告)日：2001-06-13

申请号：EP99953560.2

申请日：1999-08-20

Applicant: Infineon Technologies AG

Inventor： MIERSCH, Ekkehard ,  MUFF, Simon ,  POHL, Jens

IPC: G11C7/10

CPC classification number: G11C8/12 ,  G06F13/1684

Abstract: The invention relates to a memory system, comprising data lines (15, 25, 35) for transmitting data between memory modules (30) and at least one control unit (5, 10, 20). According to the invention, the memory system is configured in such a way that it has at least one central control unit (5) and at least one group control unit (10), said group control unit (10) having at least one first data line (15) for connecting the group control unit (10) to the central control unit (5) and second data lines (25) for connecting a group of memory modules (30) to the group control unit (10).

Abstract translation: 本发明涉及一种存储器系统，包括用于在存储器模块（30）与至少一个控制单元（5,10,20）之间传输数据的数据线（15,25,35）。 根据本发明，存储器系统被配置为使得其具有至少一个中央控制单元（5）和至少一个组控制单元（10），所述组控制单元（10）具有至少一个第一数据 （10）连接到中央控制单元（5）的线路（15）以及用于将一组存储器模块（30）连接到组控制单元（10）的第二数据线路（25）。

公开(公告)号：EP1094467A2

公开(公告)日：2001-04-25

申请号：EP00122535.8

申请日：2000-10-16

Applicant: MOTOROLA, INC.

Inventor： Naji, Peter K.

IPC: G11C11/15 ,  G11C8/00

CPC classification number: G11C11/15 ,  G11C8/12 ,  G11C8/16

Abstract: Processing equipment with embedded MRAMs, and a method of fabricating, including a data processing device (10) fabricated on a semiconductor chip with MRAM cells fabricated on the chip to form one to all of the memories on the chip. Also included is a dual bank memory (31,32) in communication with the data processing (10) device and circuitry coupled to the data processing device and the dual bank memory for providing simultaneous read access to the dual bank memory.

Abstract translation: 具有嵌入式MRAM的处理设备以及包括在半导体芯片上制造的数据处理设备（10）的方法，该半导体芯片上制造有MRAM单元以在芯片上形成一个到所有的存储器。 还包括与数据处理设备（10）通信的双组存储器（31,32）和耦合到数据处理设备和双组存储器的电路，用于提供对双组存储器的同时读取访问。