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    Analog sensing of memory cells in a solid-state memory device
    3.
    发明公开
    Analog sensing of memory cells in a solid-state memory device 审中-公开
    在einer Feststoffspeichervorrichtung分析Erfassung von Speicherzellen

    公开(公告)号：EP2469539A1

    公开(公告)日：2012-06-27

    申请号：EP12001345.3

    申请日：2008-07-14

    申请人： Micron Technology, Inc.

    发明人： Sarin, Vishal ,  Hoei, Jung-Sheng ,  Roohparvar, Frankie, F.

    IPC分类号： G11C8/00 ,  G11C29/00 ,  G11C27/02 ,  G11C11/56 ,  G11C16/28

    CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C27/005 ,  G11C27/02 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： The memory device comprises: a series string of memory cells; a current sensing circuit coupled to a bit line of the series string of memory cells and configured to generate a sense amplifier control signal in response to detection of a bit line current generated by a read threshold voltage on a word line of the series string of memory cells; a voltage generator coupled to the word line and configured to generate a ramped voltage on which the read threshold voltage is located; and a sample/hold and comparator circuit (802) coupled to the bit line, the circuit comprising: a first capacitor (813) coupled to the voltage generator through a first switch (810) and configured to store a representation of the read threshold voltage; a first operational amplifier-driver (820) coupled to the first capacitor (813) and configured to output data representative of the read threshold voltage; a second capacitor (805) coupled to the voltage generator through a second switch (806) and configured to store a representation of a target threshold voltage; and a second operational amplifier-driver (807) coupled to the second capacitor (805) and to the output of the first operational amplifier driver (820), the second operational amplifier-driver (807) configured to generate an inhibit signal in response to the sense amplifier control signal and a comparison of the representation of the read threshold voltage with the representation of the target voltage.

    摘要翻译： 存储器件包括：一串串存储器单元; 耦合到串联串存储器单元的位线的电流感测电路，并且被配置为响应于由串行串存储器的字线上的读取阈值电压产生的位线电流的检测而产生读出放大器控制信号 细胞; 电压发生器，其耦合到所述字线并且被配置为产生所述读取阈值电压所在的斜坡电压; 以及耦合到所述位线的采样/保持和比较器电路（802），所述电路包括：通过第一开关（810）耦合到所述电压发生器的第一电容器（813），并且被配置为存储所读取的阈值电压 ; 耦合到所述第一电容器（813）并且被配置为输出表示所述读阈值电压的数据的第一运算放大器驱动器（820） 第二电容器（805），其通过第二开关（806）耦合到所述电压发生器，并且被配置为存储目标阈值电压的表示; 以及耦合到所述第二电容器（805）和所述第一运算放大器驱动器（820）的输出的第二运算放大器驱动器（807），所述第二运算放大器驱动器（807）被配置为响应于 读出放大器控制信号和读取阈值电压的表示与目标电压的表示的比较。

    Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus for demarcating memory states of the cell
    4.
    发明公开
    Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus for demarcating memory states of the cell 失效
    存储装置，包括可编程非易失性多位和装置用于划定细胞的存储器状态

    公开(公告)号：EP2273507A3

    公开(公告)日：2012-01-11

    申请号：EP10185592.2

    申请日：1997-12-11

    申请人： BTG International Inc

    发明人： Banks, Gerald J.

    IPC分类号： G11C11/56

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/16 ,  G11C16/32 ,  G11C2211/5634 ,  G11C2211/5642

    摘要： Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both pets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

    Method of programming memory
    10.
    发明公开
    Method of programming memory 审中-公开
    一种用于编程的存储器的方法

    公开(公告)号：EP1503384A2

    公开(公告)日：2005-02-02

    申请号：EP04250188.2

    申请日：2004-01-15

    申请人： Macronix International Co., Ltd.

    发明人： Yeh, Chih Chieh ,  Lai, Han Chao ,  Tsai, Wen Jer ,  Lu, Tao Cheng ,  Lu, Chih Yuan

    IPC分类号： G11C11/56

    CPC分类号： G11C17/14 ,  G11C11/5692 ,  G11C2211/5634 ,  G11C2211/5641 ,  H01L27/101

    摘要： A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.