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公开(公告)号：EP4261550A1
公开(公告)日：2023-10-18
申请号：EP23163828.9
申请日：2023-03-23
Applicant: STMicroelectronics International N.V.
Inventor： JAIN, Sandeep , GEORGE, Jeena Mary
IPC: G01R31/3181 , G01R31/3185
Abstract: In an embodiment, an integrated circuit (700) includes: a voting circuit (706) including N scan flip-flops (402, 404, 406), where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop (402) and a second scan flip-flop (406), where an output of the first scan flip-flop (402) is coupled to a scan input of the second scan flip-flop (406); a scan chain (720) including the N scan flip-flops (402, 404, 406) of the voting circuit (706), and third (704) and fourth (708) scan flip-flops, the scan chain configured to receive a scan enable signal (scan_en); and a scan enable control circuit (550, 552) configured to control a scan enable input of the first (402) or second (406) scan flip-flops based on the scan enable signal (scan_en) and based on a scan input of the third scan flip-flop (704) or an output of the fourth scan flip-flop (708).
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公开(公告)号：EP4254050A1
公开(公告)日：2023-10-04
申请号：EP23162790.2
申请日：2023-03-20
Applicant: STMicroelectronics International N.V.
Inventor： NESTOROVIC, Nenad , SCHMIDT, Jack
IPC: G02B27/09
Abstract: An optical module for a laser scanning projector, including: a first lens doublet (12) configured to receive a combined laser beam, the first lens doublet comprising a first plano-concave lens (13), which has an upstream surface with a concave cross section and a downstream surface with a planar cross section, and a first plano-convex lens (14) downstream of the first plano-concave lens (13) having an upstream surface with a planar cross section and a downstream surface with a convex cross section; a second lens doublet (15) downstream of the first lens doublet (12) and including a first concave lens (16) and a second lens (17) downstream of the first concave lens (16) having an upstream surface with a convex cross section and a downstream surface with a paraboloid cross section; a spherical lens (25) downstream of the second lens doublet (15) and having an upstream surface with a concave cross section and a downstream surface with a convex cross section; a third lens doublet downstream (26) of the spherical lens (25) and including a second concave lens (27) and a convex lens (28) downstream of the second concave lens (27); and a second plano-concave lens (29) having an upstream surface with a planar cross section and a downstream surface with a concave cross section. The first lens doublet (12), the second lens doublet (15), the spherical lens (25), the third lens doublet (26) and the second plano-concave lens (29) cooperate to shape the combined laser beam to have high-divergence along a first axis and a low-divergence along a second axis.
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公开(公告)号：EP4249928A1
公开(公告)日：2023-09-27
申请号：EP23160225.1
申请日：2023-03-06
Applicant: STMicroelectronics International N.V.
IPC: G01R31/3185
Abstract: In an embodiment, a method for performing scan testing includes: generating first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals; providing the first and second scan clock signals to first (524) and second (514) scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal (scan_en) is asserted, and respective first capture pulses when the scan enable signal (scan_en) is deasserted, where the first shift pulse of the first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals correspond to a first clock pulse of a first clock signal (CLK slow ), where the first capture pulse of the first scan clock signal (CLK scan_lf ) corresponds to a second clock pulse of the first clock signal (CLK slow ), and where the first capture pulse of the second scan clock signal (CLK scan_hf ) corresponds to a first clock pulse of a second clock signal (CLK fast ) different from the first clock signal (CLK slow ).
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公开(公告)号：EP4236076A1
公开(公告)日：2023-08-30
申请号：EP23157338.7
申请日：2023-02-17
Applicant: STMicroelectronics International N.V.
Inventor： KAUSHIK, Sandeep , GARG, Paras
IPC: H03K19/0185 , H04L25/02
Abstract: A Low Voltage Differential Signaling, LVDS, transmitter includes driver circuit (110) with a first transistor (P1), a second transistor (P2), a third transistor (N1), a fourth transistor (N2), a first resistor (R1), and a second resistor (R2). The first transistor (P1) is coupled between a first node (112) and first output (PadN). The second transistor (P2) is coupled between the first node (112) and a second output (PadP). The third transistor (N1) is coupled between the first output (PadN) and a second node (114). The fourth transistor (N4) is coupled between the second output (PadP) and the second node (114). The first resistor (R1) is coupled between the first output and a common mode node (Vcm). The second resistor (R2) is coupled between the second output and the common mode node. A pre-driver circuit (120) generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal (Data). A controlled timing delay is applied to the timing of logic state transistors for the control signals.
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公开(公告)号：EP4227758A1
公开(公告)日：2023-08-16
申请号：EP23155843.8
申请日：2023-02-09
Applicant: STMicroelectronics International N.V.
Inventor： BAL, Ankur , GUPTA, Sharad , JAIN, Anupam
Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.
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Patent Agency Ranking
公开(公告)号：EP4174692A1
公开(公告)日：2023-05-03
申请号：EP22201273.4
申请日：2022-10-13
Inventor： GOYAL, Avneep Kumar , SZURMANT, Thomas
Abstract: A system on a chip including a first-port controller (106) for a first development port (102) configured to receive a first development tool and a second-port controller (108) for a second development port (104) configured to receive a second development tool. The system on a chip further including a central controller (110) in communication with the first-port controller (106), the second-port controller (108), and a security subsystem (112). The central controller (110) being configured to manage authentication exchanges between the security subsystem (112) and the first development tool and authentication exchanges between the security subsystem (112) and the second development tool.
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公开(公告)号：EP4174502A1
公开(公告)日：2023-05-03
申请号：EP22201456.5
申请日：2022-10-13
Applicant: STMicroelectronics International N.V.
Inventor： SRINIVASAN, V Narayanan , SHARMA, Manish , GUPTA, Tripti
IPC: G01R31/3185
Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains (PDO, PD1, PD2, ED) using a same scan chain compressor-decompressor circuit (80, 5) may be performed. Also disclosed herein are integrated circuit chips (1, 1') having test circuitry designed such that independently selectable testing of different power domains (PDO, PD1, PD2, ED) using multiple different scan chain compressor-decompressor circuits (80, 5) may be performed.
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公开(公告)号：EP4141677A1
公开(公告)日：2023-03-01
申请号：EP22192295.8
申请日：2022-08-26
Inventor： SHARMA, Vivek Mohan , COLOMBO, Roberto
Abstract: A processing system is described. The processing system comprises an error detection circuit (46) configured to receive data bits (DATA) and ECC bits. The error detection circuit (46) calculates further ECC bits as a function of the data bits (DATA) and generates a syndrome (SYN) by comparing the calculated ECC bits with the received ECC bits. When the syndrome (SYN) corresponds to one of N + K single bit-flip reference syndromes, the error detection circuit (46) asserts a first error signal (ERR 1 ), and asserts one bit of a bit-flip signature (SIG) corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
The processing system further comprises a test circuit (48) configured to provide, during a test-mode (TM), a sequence of patterns (PAT) to the error detection circuit (46), each pattern (PAT) comprising data bits (DATA) and ECC bits. Specifically, the test circuit (48) obtains a first pattern (PAT) without ECC errors, provides the first pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is de-asserted and all bits of the bit-flip signature (SIG) are de-asserted. Moreover, the test circuit (48) obtains a sequence of N + K further bit-flip signatures (FSIG), each further bit-flip signature (SIG) having asserted a single bit. Moreover, the test circuit obtains (1008, 1014) for each further bit-flip signature (FSIG) a respective second pattern (PAT), wherein each second pattern (PAT) corresponds to a pattern having a single bit flipped with respect to a reference pattern at the positions of the single asserted bit of the respective further bit-flip signature (FSIG). The test circuit provides each second pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is asserted and the bit-flip signature (SIG) corresponds to the respective further bit-flip signature.-
公开(公告)号：EP4116974A1
公开(公告)日：2023-01-11
申请号：EP22182464.2
申请日：2022-07-01
Applicant: STMicroelectronics International N.V.
Inventor： RAWAT, Harsh , DHORI, Kedar Janardan , KUMAR, Promod , CHAWLA, Nitin , AYODHYAWASI, Manuj
IPC: G11C5/00 , G11C7/04 , G11C11/412 , G11C11/419 , G11C7/10
Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.
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公开(公告)号：EP4107854A1
公开(公告)日：2022-12-28
申请号：EP21704570.7
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： LEMOINE, Renaud , OUYAHIA, Samia , WILHELM, Eric , BOYAVALLE, Christophe
IPC: H03F1/02
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