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公开(公告)号：EP1653747B1
公开(公告)日：2015-08-19
申请号：EP05022773.5
申请日：2005-10-19
IPC分类号： H04N21/43
CPC分类号： H04N21/4305
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公开(公告)号：EP4462467A1
公开(公告)日：2024-11-13
申请号：EP24169742.4
申请日：2024-04-11
IPC分类号： H01L21/48 , H01L21/56 , H01L23/495 , H01L23/00
摘要： A plurality of semiconductor dice is arranged onto a first surface of a common electrically conductive substrate (12). The common electrically conductive substrate (12) has a second surface opposite the first surface and comprises a plurality of substrate portions (12A, 12B) and elongated sacrificial connecting bars (CB) extending between adjacent substrate portions (12B). Insulating material (100) is coated on the second surface of the elongate sacrificial connecting bars (CB). Solder material (18) is grown on the second surface of the common electrically conductive substrate (12). The insulating material (100) counters growth of the solder material on the second surface of the elongate sacrificial connecting bars (CB). Singulated individual semiconductor devices are provided by cutting the common electrically conductive substrate (12) having the plurality of semiconductor dice arranged onto the first surface thereof along the length of the elongate sacrificial connecting bars (CB) having the insulating material (100) coated on its second surface.
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公开(公告)号：EP4462416A1
公开(公告)日：2024-11-13
申请号：EP24173017.5
申请日：2024-04-29
摘要： La présente description concerne un système comprenant :
- un microcontrôleur (106) comprenant un réseau de neurones (120) ;
- un capteur à temps de vol (104) configuré pour effectuer une capture d'une scène comprenant un utilisateur, et comprenant une pluralité de pixels, la capture comprenant, pour chaque pixel, la mesure d'une distance à l'utilisateur et d'une valeur de signal, le capteur étant en outre configuré pour calculer une valeur d'écart type associé à la valeur de distance et une valeur d'écart-type associé à la valeur de signal et une valeur de confiance, le capteur étant en outre configuré pour fournir les valeurs au réseau,
le réseau étant configuré pour générer, sur la base des valeurs, une estimation d'une direction associée à l'utilisateur, le système comprenant en outre un écran (102), le microcontrôleur étant configuré pour contrôler l'écran, ou un autre circuit, sur la base de l'estimation.-
74.发明公开
公开(公告)号：EP4459493A1
公开(公告)日：2024-11-06
申请号：EP24172620.7
申请日：2024-04-26
发明人： PALLARDY, Loic , BERTHELOT, Vincent
摘要： Le système sur puce (SOC) comporte un contrôleur de mémoire (CNTMEM) adapté pour recevoir des transactions (TR1, TR2) contenant des informations de transaction (TINF) définissant un accès à une mémoire (MEM), le contrôleur de mémoire (CNTMEM) étant configuré pour stocker les informations de transaction dans un registre de commande (REG), et pour piloter l'accès à la mémoire (MEM) à partir du contenu dudit registre de commande (REG). Le contrôleur de mémoire (CNTMEM) comporte des moyens de vérification (CMP) configurés pour conditionner l'accès à la mémoire en fonction d'une comparaison entre les informations de transaction stockées dans le registre de commande (REG) et une liste d'informations spéciales (LST) définissant des transactions spéciales.
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公开(公告)号：EP4447320A1
公开(公告)日：2024-10-16
申请号：EP23305555.7
申请日：2023-04-13
发明人： GONTHIER, Laurent , LI, Jimmy
摘要： The present disclosure relates to a control circuit (210) of a triac (TR201) or thyristor having its driving reference terminal connected to a first reference node (IN202) and coupled to a voltage rectifier (202) comprising at least a semiconductor device (D204) connected between the first reference node (IN202) and a second reference node (GND-DC-200)of the control circuit comprising:
- A first bipolar transistor (TB210);
- A driving circuit of said first transistor (TB210) referenced to the second reference node (GND-DC-200).-
76.发明公开
公开(公告)号：EP4447310A1
公开(公告)日：2024-10-16
申请号：EP24169785.3
申请日：2024-04-11
摘要： A safety circuit (13) for a gate driver device (14) receives PWM driving signals (INH, INL), a system supply voltage (VDD), as well as first (STO1_INT) and second (STO2_INT) safety signals. The circuit (13) includes a first logic circuit (202, 213) configured to propagate the PWM driving signals (INH, INL) to produce gate driving signals (INHg, INLg) if the first safety signal (STO1_INT) is de-asserted, and disable propagation of the PWM driving signals (INH, INL) and de-assert the gate driving signals (INHg, INLg) if the first safety signal (STO1_INT) is asserted. The circuit (13) includes a second logic circuit (216) configured to couple a power supply output node (502) to the system supply voltage (VDD) to produce a driver supply voltage (VSUPPLY) if the second safety signal (STO2_INT) is de-asserted, and decouple the power supply output node (502) from the system supply voltage (VDD) if the second safety signal (STO2_INT) is asserted.
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公开(公告)号：EP4443174A1
公开(公告)日：2024-10-09
申请号：EP24166167.7
申请日：2024-03-26
CPC分类号： G01R15/202 , G01R15/207 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3128
摘要： An integrated circuit current sensing device (10), comprises an insulating encapsulation (20) that encapsulates a semiconductor die (14) having integrated therein a Hall current sensor (HS) configured to measure an electric current (I) flowing adjacent an active surface of the semiconductor die (14). Embedded in the insulating encapsulation (20) there is provided an electrically conductive trace (100) having opposed ends providing therebetween a current flow path adjacent the active surface of the semiconductor die (14).
First electrically conductive formations (101) extend through the insulating encapsulation (20) towards the opposed ends of the electrically conductive trace (100) embedded in the insulating encapsulation (20, 20', 20"). The first electrically conductive formations (101) are configured to cause (101) an electrical current subject to measurement to flow in the aforesaid current flow path adjacent the active surface of the semiconductor die (14). Second electrically conductive formations (182, 120, 121) extend through the insulating encapsulation (20) towards the active surface of the semiconductor die (14), the second electrically conductive formations (181, 182, 121) are configured to activate the Hall current sensor (HS) integrated in the semiconductor die (14).-
78.发明公开
公开(公告)号：EP4428759A3
公开(公告)日：2024-10-09
申请号：EP24155570.5
申请日：2024-02-02
发明人： ROSSI, Michele , DESOLI, Giuseppe , BOESCH, Thomas
IPC分类号： G06N3/065 , G06N3/0464 , G06F13/40
CPC分类号： G06N3/065 , G06N3/0464 , G06F13/4022
摘要： A hardware accelerator (110) includes processing elements (172) of a neural network, each processing element having a memory (104); a stream switch (155); stream engines (150) coupled to functional circuits (102, 160, 165, 180) via the stream switch (155), wherein the stream engines (150), in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits (102, 160, 165, 180); a first system bus interface (158) coupled to the stream engines (150); a second system bus interface (184) coupled to the processing elements (172); and mode control circuitry (176), which, in operation, sets respective modes of operation for the plurality of processing elements (172). The modes of operation include: a compute mode of operation in which the processing element (172) performs computing operations using the memory (104) associated with the processing element; and a memory mode of operation in which the memory (104) associated with the processing element (172) performs memory operations, bypassing the stream switch (155), via the second system bus interface (184).
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公开(公告)号：EP4440035A1
公开(公告)日：2024-10-02
申请号：EP24165232.0
申请日：2024-03-21
CPC分类号： G09C1/00 , G06F2207/727120130101 , G06F7/02 , G06F11/1004 , H04L2209/2620130101 , H04L9/3239
摘要： La présente description concerne un procédé de vérification d'une première donnée par une première formule mathématique : k=XORi=1NXi dans laquelle :
- k représente ladite première donnée ;
- XORi=1N représente l'application d'une première fonction logique OU EXCLUSIF à N entrées, N étant un entier ; et
- Xi représente N deuxièmes données (X1, ..., XN) indépendantes de la première donnée, i variant de 1 à N,
ledit procédé comprenant une étape de vérification (404) d'une deuxième formule mathématique : CRCk=XORi=1NCRCXi dans laquelle CRC( ) représente l'image d'une donnée par une deuxième fonction de contrôle de redondance cyclique linéaire par rapport à la fonction logique OU EXCLUSIF.-
公开(公告)号：EP4439677A1
公开(公告)日：2024-10-02
申请号：EP24315107.3
申请日：2024-03-26
发明人： Iucolano, Ferdinando , Chini, Alessandro , Castagna, Maria Eloisa , Constant, Aurore , Tringali, Cristina
IPC分类号： H01L29/778 , H01L21/337 , H01L29/10 , H01L29/41 , H01L29/20
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/404 , H01L29/1066 , H01L29/66462
摘要： The HEMT device (20) has a body (22) including a heterostructure (25) configured to generate a 2-dimensional charge-carrier gas (30, 49); and a gate structure (33) which extends on a top surface (22A) of the body and is biasable to electrically control the 2-dimensional charge-carrier gas. The gate structure has a channel modulating region (40) of semiconductor material; a functional region (41) of semiconductor material; and a gate contact region (42) of conductive material. The functional region and the gate contact region extend on a top surface (40A) of the channel modulating region and the gate contact region is arranged laterally with respect to the functional region. The channel modulating region (40) has a different conductivity type with respect to the functional region (41).
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