公开(公告)号：EP4407327A1

公开(公告)日：2024-07-31

申请号：EP24150870.4

申请日：2024-01-09

申请人： STMicroelectronics International N.V.

发明人： SRINIVASAN, V Narayanan ,  SRIVASTAVA, Umesh Chandra ,  VATS, Shiv Kumar ,  SHARMA, Manish

IPC分类号： G01R31/3185

CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318536

摘要： According to an embodiment, a digital circuit (400) includes an OR gate (402) and a flip-flop (406). The OR gate (402) includes a first input and a second input. The first input of the OR gate is coupled to a control signal (CTRL), and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit (400). The first input of the OR gate (402) is configured to be pulled low by the control signal (CTRL) in response to setting the digital circuit (400) in a configuration to test the uncovered functional combination logic. The flip-flop (406) includes a reset pin (R) or a set pin (S) coupled to the output of the OR gate (402). The output of the flip-flop (406) is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit (400).

公开(公告)号：EP4249928A1

公开(公告)日：2023-09-27

申请号：EP23160225.1

申请日：2023-03-06

申请人： STMicroelectronics International N.V.

发明人： SRINIVASAN, V Narayanan ,  SHARMA, Manish ,  VATS, Shiv Kumar ,  SRIVASTAVA, Umesh Chandra

IPC分类号： G01R31/3185

摘要： In an embodiment, a method for performing scan testing includes: generating first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals; providing the first and second scan clock signals to first (524) and second (514) scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal (scan_en) is asserted, and respective first capture pulses when the scan enable signal (scan_en) is deasserted, where the first shift pulse of the first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals correspond to a first clock pulse of a first clock signal (CLK slow ), where the first capture pulse of the first scan clock signal (CLK scan_lf ) corresponds to a second clock pulse of the first clock signal (CLK slow ), and where the first capture pulse of the second scan clock signal (CLK scan_hf ) corresponds to a first clock pulse of a second clock signal (CLK fast ) different from the first clock signal (CLK slow ).

公开(公告)号：EP4036590A2

公开(公告)日：2022-08-03

申请号：EP22151334.4

申请日：2022-01-13

申请人： STMicroelectronics International N.V.

发明人： SRINIVASAN, V Narayanan ,  VATS, Shiv Kumar ,  GUPTA, Tripti

IPC分类号： G01R31/3185

摘要： In an embodiment, a method for performing scan includes: entering scan mode (1202); receiving a test pattern (1204); applying (1208) the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating (1212) an output of the first scan chain to detect faults.