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    METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR
    2.
    发明公开
    METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR 审中-公开

    公开(公告)号：EP4064002A1

    公开(公告)日：2022-09-28

    申请号：EP22161469.6

    申请日：2022-03-10

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  HARESHBHAI NIRANJANI, Mayankkumar ,  GARG, Gourav

    IPC分类号： G06F1/26

    摘要： A method to bypass a voltage regulator (1010) of a system on a chip (SOC) (1000) comprising powering a first power domain (1002) of the SOC using a voltage regulator (1010); powering a second power domain (1004) of the SOC using the voltage regulator (1010); coupling a third power domain (1006) of the SOC with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator (1010); coupling the first and second power domains to the external voltage source; turning OFF the voltage regulator (1010) of the SOC after coupling the first power domain (1002) of the SOC (1000) and the second power domain (1004) of the SOC (1000) to the external voltage source; and powering the first power domain (1002) of the SOC (1000), the second power domain (1004) of the SOC (1000), and the third power domain (1006) of the SOC (1000) with the external voltage source, the external voltage source bypassing the voltage regulator (1010).

    EFFECTIVE SCAN COVERAGE
    3.
    发明公开
    EFFECTIVE SCAN COVERAGE 审中-公开

    公开(公告)号：EP4407327A1

    公开(公告)日：2024-07-31

    申请号：EP24150870.4

    申请日：2024-01-09

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  SRIVASTAVA, Umesh Chandra ,  VATS, Shiv Kumar ,  SHARMA, Manish

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318536

    摘要： According to an embodiment, a digital circuit (400) includes an OR gate (402) and a flip-flop (406). The OR gate (402) includes a first input and a second input. The first input of the OR gate is coupled to a control signal (CTRL), and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit (400). The first input of the OR gate (402) is configured to be pulled low by the control signal (CTRL) in response to setting the digital circuit (400) in a configuration to test the uncovered functional combination logic. The flip-flop (406) includes a reset pin (R) or a set pin (S) coupled to the output of the OR gate (402). The output of the flip-flop (406) is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit (400).

    RESET AND SAFE STATE LOGIC GENERATION IN DUAL POWER FLOW DEVICES
    4.
    发明公开
    RESET AND SAFE STATE LOGIC GENERATION IN DUAL POWER FLOW DEVICES 审中-公开

    公开(公告)号：EP4187789A1

    公开(公告)日：2023-05-31

    申请号：EP22203526.3

    申请日：2022-10-25

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  HARESHBHAI NIRANJANI, Mayankkumar ,  KUMAR, Dhulipalla Phaneendra ,  GARG, Gourav ,  BANZAL, Sourabh

    IPC分类号： H03K19/00 ,  G06F1/00 ,  G06F1/3203 ,  G06F1/3287

    摘要： An electric device (100) includes: a first power domain (101); a second power domain (103); a third power domain (105), where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths (111, 112, 113, 114, 115, 116) that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal (ISO_CTRLS) for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

    CIRCUIT AND METHOD FOR SCAN TESTING
    7.
    发明公开
    CIRCUIT AND METHOD FOR SCAN TESTING 审中-公开

    公开(公告)号：EP4249928A1

    公开(公告)日：2023-09-27

    申请号：EP23160225.1

    申请日：2023-03-06

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  SHARMA, Manish ,  VATS, Shiv Kumar ,  SRIVASTAVA, Umesh Chandra

    IPC分类号： G01R31/3185

    摘要： In an embodiment, a method for performing scan testing includes: generating first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals; providing the first and second scan clock signals to first (524) and second (514) scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal (scan_en) is asserted, and respective first capture pulses when the scan enable signal (scan_en) is deasserted, where the first shift pulse of the first (CLK scan_lf ) and second (CLK scan_hf ) scan clock signals correspond to a first clock pulse of a first clock signal (CLK slow ), where the first capture pulse of the first scan clock signal (CLK scan_lf ) corresponds to a second clock pulse of the first clock signal (CLK slow ), and where the first capture pulse of the second scan clock signal (CLK scan_hf ) corresponds to a first clock pulse of a second clock signal (CLK fast ) different from the first clock signal (CLK slow ).

    SCAN CIRCUIT AND METHOD
    9.
    发明公开
    SCAN CIRCUIT AND METHOD 审中-公开

    公开(公告)号：EP4036590A2

    公开(公告)日：2022-08-03

    申请号：EP22151334.4

    申请日：2022-01-13

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  VATS, Shiv Kumar ,  GUPTA, Tripti

    IPC分类号： G01R31/3185

    摘要： In an embodiment, a method for performing scan includes: entering scan mode (1202); receiving a test pattern (1204); applying (1208) the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating (1212) an output of the first scan chain to detect faults.

    ISOLATION ENABLE TEST COVERAGE FOR MULTIPLE POWER DOMAINS
    10.
    发明公开
    ISOLATION ENABLE TEST COVERAGE FOR MULTIPLE POWER DOMAINS 审中-公开

    公开(公告)号：EP3919923A1

    公开(公告)日：2021-12-08

    申请号：EP21174165.7

    申请日：2021-05-17

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan

    IPC分类号： G01R31/317 ,  G01R31/3185

    摘要： A method of testing a multiple power domain device (100) includes sending a control signal from a test controller (118) powered by a switchable power domain (SWi, 110) to a non-scan test data register powered by an always on power domain (AO, 102). The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain (SWi, 110) and an input of the always on domain (102) and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.