公开(公告)号：EP0811934A2

公开(公告)日：1997-12-10

申请号：EP97303804.5

申请日：1997-06-04

申请人： Compaq Computer Corporation

发明人： Pettey, Christopher J. ,  Maclaren, John M.

IPC分类号： G06F13/40

CPC分类号： G06F13/4045

摘要： A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

摘要翻译： 计算机系统包括第一数据总线上的数据存储装置，第二数据总线上的装置和能够存储用于从第二数据总线传送到第一数据总线的多个数据事务的桥接装置。 桥接器件包括预先分配给桥接器中保持的一个事务的第一数据存储缓冲器，以及缓冲器管理元件，当与事务相关联的数据溢出第一个时，缓冲器管理元件必要时将数据存储缓冲器分配给数据事务 数据存储缓冲区。

公开(公告)号：EP0811933A2

公开(公告)日：1997-12-10

申请号：EP97303803.7

申请日：1997-06-04

申请人： Compaq Computer Corporation

发明人： Goodrum, Alan L. ,  Maclaren, John M. ,  Culley, Paul R.

IPC分类号： G06F13/40

CPC分类号： G06F13/4059

摘要： A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

摘要翻译： 计算机系统包括第一数据总线上的第一设备，第二数据总线上的第二设备以及将数据从第一设备传送到第二设备并将所请求的数据返回给第一设备的桥接设备。 桥接器件包括第一数据存储缓冲器，其存储在第一请求期间由第一器件请求的数据，以及第二数据缓冲器，其在第二请求期间同时存储由第一器件请求的数据。

公开(公告)号：EP0811927A2

公开(公告)日：1997-12-10

申请号：EP97303791.4

申请日：1997-06-04

申请人： Compaq Computer Corporation

发明人： MacLaren, John M. ,  Goodrum, Alan L.

IPC分类号： G06F13/40

CPC分类号： G06F13/4036

摘要： A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher priority transaction and transactions initiated before the higher priority transaction, and a controller that selects transactions from the execution queue to be completed on one of the data buses.

摘要翻译： 计算机系统包括第一数据总线上的第一设备，第二数据总线上的第二设备以及在两个设备之间传送数据事务的桥接设备。 桥接器件包括仅存储较高优先级事务的执行队列和在较高优先级事务之前启动的事务，以及从执行队列中选择要在其中一条数据总线上完成的事务的控制器。

公开(公告)号：EP0802487A2

公开(公告)日：1997-10-22

申请号：EP97302535.6

申请日：1997-04-14

申请人： Compaq Computer Corporation

发明人： Sides, Chi Kim ,  McKenzie, Philip J. ,  Basile, Barry S.

IPC分类号： G06F13/40

CPC分类号： G06F13/4081 ,  H02H9/004

摘要： A protection circuit 116 for a computer system 110 having PCI expansion cards 120 and PCI expansion slots 118 with multiple power rails 312,322;314,328;318,324;320,326 for supplying power to the PCI expansion cards is disclosed. The protection circuit includes a current monitor 212 that monitors the current levels drawn by the PCI expansion card at each power rail. An inrush current controller 330/332/334 controls the initial current applied to each of the power rails when an expansion card is initially inserted into an expansion slot. A voltage monitor 212 monitors the voltage levels applied to selected power rails and a disconnector 210 disconnects the power to the PCI expansion slot when either the current level drawn by the PCI expansion card at any of the power rails goes beyond a selected range or when the voltage levels at any of the selected monitored power rails are below a selected threshold, or when commanded to by the computer system.

摘要翻译： 公开了一种用于具有PCI扩展卡120的计算机系统110的保护电路116和具有用于向PCI扩展卡供电的多个电源轨312,322,314,328,318,324,320,326的PCI扩展槽118。 保护电路包括电流监视器212，其监视由PCI扩展卡在每个电力轨上绘制的电流水平。 浪涌电流控制器330/332/334控制当扩展卡最初插入到扩展槽中时施加到每个电源轨的初始电流。 电压监视器212监视施加到所选择的电源轨的电压电平，并且当PCI扩展卡在任何电源轨下拉出的电流水平超过所选择的范围时，断路器210断开与PCI扩展槽的电力，或者当 所选择的所监视的电力轨道中的任何一个电压电平都低于选定的阈值，或者由计算机系统命令。

公开(公告)号：EP0794480A1

公开(公告)日：1997-09-10

申请号：EP97301417.8

申请日：1997-03-04

申请人： Compaq Computer Corporation

发明人： Fritz, Brian C.

IPC分类号： G06F1/26

CPC分类号： H02J7/0004 ,  G06F1/263 ,  Y10T307/625

摘要： The present invention relates to circuitry for selecting a master battery pack for supplying power to a computer system capable of incorporating multiple battery packs. A bi-directional master battery signal is communicated to the microcontroller of each installed battery pack and arbitration circuitry contained within the host computer system. The master battery signal operates in conjunction with a serial communications interface between each of the installed battery packs and the host computer system. Battery status information is communicated to the host computer system via the serial communications interface, and the host computer system then selects a master battery pack. The battery pack selected to be the master asserts the master battery signal while all other battery packs monitor this signal waiting for it to be deasserted. Other battery packs utilize the master battery signal to control their own charge and discharge circuitry. Deassertion of the master battery signal denotes that the master battery pack is no longer capable of supplying power to the host computer system and the master battery pack arbitration process is repeated.

摘要翻译： 本发明涉及用于选择用于向能够并入多个电池组的计算机系统供电的主电池组的电路。 双向主电池信号被传送到每个安装的电池组的微控制器和包含在主计算机系统内的仲裁电路。 主电池信号与每个安装的电池组和主机系统之间的串行通信接口一起操作。 电池状态信息通过串行通信接口传送到主计算机系统，然后主计算机系统选择主电池组。 选择为主机的电池组会断开主电池信号，而所有其他电池组都会监视此信号，等待其被取消置位。 其他电池组利用主电池信号来控制自己的充电和放电电路。 主电池信号的取消表示主电池组不再能够向主机系统供电，并且重复主电池组仲裁过程。

公开(公告)号：EP0788630A1

公开(公告)日：1997-08-13

申请号：EP94904810.0

申请日：1993-12-01

申请人： Compaq Computer Corporation

发明人： CLARK, Ted, H. ,  MALISEWSKI, Steven, C. ,  COOPER, Patrick, R. ,  CROSSWY, William, Caldwell ,  CROCHET, Larry, J.

IPC分类号： G06F1 ,  G06F12 ,  G06F15 ,  G06F17 ,  G06Q10

CPC分类号： G06F17/30176 ,  G06F1/1626 ,  G06F1/1632 ,  G06F1/1656 ,  G06F1/166 ,  G06F1/1698 ,  G06F15/0225 ,  G06F15/0266 ,  G06Q10/109 ,  Y10S707/99952 ,  Y10S707/99953

摘要： A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed. Several synchronization tehcniqques are utilized to keep track of different types of files. In addition, while communication is established the handheld computer can enter a remote control mode, allowing the user access to files and applications not included in the handheld computer.

公开(公告)号：EP0785501A2

公开(公告)日：1997-07-23

申请号：EP97300274.4

申请日：1997-01-17

申请人： Compaq Computer Corporation

发明人： Tran, Thanh T.

IPC分类号： G06F3/16 ,  G06F1/30

CPC分类号： H03F1/305 ,  H03F3/181 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/321 ,  H03F2203/7227 ,  H03G3/348 ,  H04R3/007

摘要： An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power has been applied to the amplifier. This control is economically accomplished using a minimal number of digital outputs.

摘要翻译： 一种用于计算机的音频功率管理系统消除了与功率的循环，在音频放大器用于在计算机相关联的可听噪声。 二极管连接在电源轨和输入到音频放大器的功率之间。 一个或多个在所述功率输入端提供去耦电容到音频放大器在电源绝缘的波动音频放大器。 该装置用于静音的信期间的放大器功率变得可用和静音立即当电力被去除以消除瞬时噪声放大器之后。 在一个，实施例的音频放大器的静噪是由FET开关来完成的。 在第二实施例中，音频放大器的静噪是由模拟开关来实现的。 此外，音频电源管理系统消除了与清醒时或把电脑进入睡眠状态相关的噪音。 之前从放大器移除功率，以减少瞬态条件的音频系统断言的扬声器静音信号。 在加电期间，电源已被施加到放大器后的扬声器静音信号被施加到放大器的期间。 这种控制在经济上是使用数字输出的最小数目来实现的。

公开(公告)号：EP0623231B1

公开(公告)日：1997-06-18

申请号：EP93903661.2

申请日：1993-01-13

申请人： Compaq Computer Corporation

发明人： ALBERS, Thomas, M. ,  EBERST, John, V. ,  FONTENOT, Darwin ,  PYRA, Richard L. ,  WELKER, Mark, W. ,  WOOD, Paul, B. ,  BRESENHAM, Jack, E.

IPC分类号： G06T11/20

CPC分类号： G06T11/203

摘要： Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.

公开(公告)号：EP0720094A3

公开(公告)日：1997-04-23

申请号：EP95309547.8

申请日：1995-12-29

申请人： Compaq Computer Corporation

发明人： Goodrum, Alan A. ,  Kotzur, Gary B. ,  Lantz, Kurt C. ,  Heinrich, David F. ,  Wilson, Jeffrey R.

IPC分类号： G06F11/00 ,  G06F15/16

CPC分类号： G06F15/177 ,  G06F1/26 ,  G06F11/1417

摘要： A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

公开(公告)号：EP0768599A1

公开(公告)日：1997-04-16

申请号：EP96307279.8

申请日：1996-10-04

申请人： COMPAQ COMPUTER CORPORATION (a Delaware corporation)

发明人： Schultz, Stephen M. ,  Thompson, Mark J.

IPC分类号： G06F3/06 ,  G06F11/10

CPC分类号： G06F11/1096 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/0689 ,  G11C29/74

摘要： A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfiguration can also be performed if the user desires to change the configuration of a particular logical volume, such as its stripe size. The disk array reconfiguration is run as a background task by firmware on a disk controller board. The reconfigure task first moves data from the source logical volume to a posting memory such as RAM memory. The reconfigure task operates one stripe at a time, with the stripe size being that of the destination logical volume. Once a stripe of data is moved into the posting memory, it is written back to corresponding locations in the destination logical volume. The reconfigure task continues until all data in the source logical volume have been moved into the destination logical volume. While the reconfigure task is working on a particular logical volume, data remains accessible to host write and read requests.

摘要翻译： 用于执行其中将源逻辑卷重新配置为目标逻辑卷的磁盘阵列的在线重新配置的系统。 如果插入新的物理驱动器或驱动器被删除，则调用磁盘阵列配置。 如果用户希望更改特定逻辑卷的配置，例如其条带大小，也可以执行重新配置。 磁盘阵列重新配置以磁盘控制器板上的固件作为后台任务运行。 重新配置任务首先将数据从源逻辑卷移动到诸如RAM存储器之类的发布存储器。 重新配置任务一次操作一个条带，条带大小是目标逻辑卷的条带大小。 一旦将数据条带移动到发布内存中，就将其写回目标逻辑卷中的相应位置。 重新配置任务继续，直到源逻辑卷中的所有数据都已移动到目标逻辑卷中。 重新配置任务正在处理特定的逻辑卷时，主机写入和读取请求的数据仍然可以访问。