公开(公告)号：EP1324380A2

公开(公告)日：2003-07-02

申请号：EP02258903.0

申请日：2002-12-20

申请人： Saifun Semiconductors Ltd

发明人： Eitan, Boaz

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L29/7923

摘要： A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, sad diffusion areas forming a channel therebetween, said channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.

公开(公告)号：EP1313138A2

公开(公告)日：2003-05-21

申请号：EP02257954.4

申请日：2002-11-19

申请人： Saifun Semiconductors Ltd.

发明人： Eitan, Boaz ,  Bloom, Ilan

IPC分类号： H01L21/336 ,  H01L21/8246

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792 ,  Y10S438/954

摘要： A method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.

摘要翻译： 一种用于保护非易失性存储器件的方法，所述方法包括形成非易失性存储器件，该非易失性存储器件包括在非导电电荷俘获层上形成的多晶硅结构，以及在该多晶硅结构的至少一部分上形成保护层， 所述保护层适于吸收具有比可见光短的波长的电磁波能量。 还公开了根据该方法构造的装置。

公开(公告)号：EP1306855A2

公开(公告)日：2003-05-02

申请号：EP02257381.0

申请日：2002-10-24

申请人： Saifun Semiconductors Ltd.

发明人： Sofer, Yair

IPC分类号： G11C16/14

CPC分类号： G11C16/3445 ,  G11C16/14

摘要： A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.

摘要翻译： 一种用于擦除非易失性存储单元阵列的方法，所述方法包括将擦除脉冲施加到所述阵列的至少一个存储单元的至少一个位，以第一擦除验证电平擦除所述至少一个位的验证，以及如果 该位已经经过第一擦除验证电平，至少将一个擦除脉冲施加到至少一个位。

公开(公告)号：EP1248260A1

公开(公告)日：2002-10-09

申请号：EP02252405.2

申请日：2002-04-03

申请人： Saifun Semiconductors Ltd

发明人： Maayan, Eduardo ,  Sofer, Yair ,  Eliyahu, Ron ,  Eitan, Boaz

IPC分类号： G11C7/06 ,  G11C7/14

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C16/28

摘要： An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.

摘要翻译： 要读取的单元（10a）连接在两个位线（BLS，BLD）之间，并且所有位线连接到Y解码器（12），将线连接到电源线（14）和感测线（16） ）。 可以生成一个输出数据的感测模块（100）使用由非选通栅极电压驱动的参考单元（104）。 包括用于感测从存储器单元接收的接地信号的方法的独立权利要求。

公开(公告)号：EP1225596A2

公开(公告)日：2002-07-24

申请号：EP01309289.5

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Bloom, Ilan ,  Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5634

摘要： A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

摘要翻译： 用于对存储器阵列的参考单元进行编程的方法包括以下步骤：用大的编程步骤对参考单元进行编程，直到参考单元的阈值电压高于临时目标水平，并以小编程步骤对所述参考单元进行编程，直到阈值 电压水平高于最终目标水平。

公开(公告)号：EP1082763A1

公开(公告)日：2001-03-14

申请号：EP99921112.1

申请日：1999-05-13

申请人： Saifun Semiconductors Ltd.

发明人： EITAN, Boaz

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A nitride programmable read only memory (NROM) cell with a pocket implant (120) self-aligned to at least one bit line junction (102, 104). Alternatively, the bit line junction(s) (102, 104) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel (100) can have a threshold voltage level implant which has a low voltage level in a central area of the channel (100) and which has a peak of high voltage level near at least one of the bit line junctions (102, 104). With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.

公开(公告)号：EP1073120A3

公开(公告)日：2001-03-07

申请号：EP00305940.9

申请日：2000-07-13

申请人： Saifun Semiconductors Ltd

发明人： Eitan, Boaz

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L21/8247 ,  H01L21/8246

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/3143 ,  H01L21/32 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/792 ,  Y10S438/954

摘要： A method of fabricating a nitride read only memory (NROM) chip creates an oxide-nitride-oxide (ONO) layer (18, 17, 20) on a substrate and etches the ONO layer within the memory portion of the chip into columns. Bit lines (12) are implanted between columns after which bit line oxides (50) are generated on top of the bit lines with the thickness of the bit line oxides being independent of the thickness of the bottom oxide. The thickness of a gate oxide layer in a periphery portion of the chip is also relatively independent of the thicknesses of the other oxides. Finally, rows of polysilicon or polysilicide (60) are formed perpendicular to and on top of the bit line oxides and the ONO columns.

公开(公告)号：EP1061580A2

公开(公告)日：2000-12-20

申请号：EP00305161.2

申请日：2000-06-19

申请人： Saifun Semiconductors Ltd.

发明人： Eitan, Boaz ,  Bloom, Ilan

IPC分类号： H01L27/02

CPC分类号： H01L27/0266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/0251

摘要： A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor (52) and an antenna (55). The protection transistor is connected between a metal line (40) having devices to be protected electrically connected thereto and a ground supply (41), where the metal line is connected to devices (50) to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna (55) is connected to a gate (G) of the protection transistor. Optionally, there is a metal ring (112, Fig. 7) around the antenna which is connected to a drain (D) of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode (118) and a parallel capacitor (120) that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.

摘要翻译： 的保护装置，其全部过程中的半导体芯片的制造过程中是活性包括保护晶体管（52）和在天线（55）。 保护晶体管被连接的设备具有的金属线（40）之间被保护与其电连接和接地电源（41），其中该金属线连接到设备（50）被保护。 天线是形成在相同的金属层的金属线的，并且控制晶体管的制造过程中的操作的保护。 天线（55）被连接到保护晶体管的栅极（G）。 任选地，存在其经由相同的金属层的金属线连接到保护晶体管的漏极（D）的金属环（112，图7）在天线周围全部。 在正常操作的芯片，保护晶体管是用于其它目的无论是主动还是被关断。关闭是由形成的第二金属层的没有连接在天线和地之间的线上设置的任一个或由反向偏置二极管 （118）和并联电容器（120）没有被连接在保护晶体管和接地的栅极之间。 本发明包括制造所述保护装置的方法。