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    Testing of integrated circuit devices on loaded printed circuit boards
    74.
    发明公开
    Testing of integrated circuit devices on loaded printed circuit boards 失效
    Prüfenvon integrierten Schaltungen auf einerbestücktenLeiterplatte。

    公开(公告)号：EP0305951A1

    公开(公告)日：1989-03-08

    申请号：EP88114058.6

    申请日：1988-08-29

    申请人： EVERETT/CHARLES CONTACT PRODUCTS INC.

    发明人： van Loan, David R. ,  Swart, Mark Andrew ,  Johnston, Charles Joseph

    IPC分类号： G01R1/04

    CPC分类号： G01R1/0425 ,  G01R31/316

    摘要： Integrated circuit (IC) packages mounted on a loaded printed circuit board (PCB) are tested by a translator module by first placing a corresponding module over each package. Each module has rows of spring contacts for releasably contacting corresponding electrical leads adjacent opposite sides of the IC package. An upper surface of the module has an array of electrically conductive test pads internally connected to corresponding contacts on the module. The test pads match an array of spring probes in the test unit. The module can be a molded plastic housing with metal leaf spring contacts, or it can comprise a composite flex-circuit material with individual contacts comprising flexible spring-like metalized plastic fingers. Contacts on the test module can releasably engage the leads on the IC package directly, or they can contact separate conductive leads on the PCB adjacent the leads on the IC package. During testing, the spring probes contact the test pads on the test modules and circuit continuity is established via the electrical connections from the spring probes through the modules to the leads adjacent the IC packages. The modules translate dense in-line spacing of leads adjacent the IC packages to the oversized in-line spacing of test pads on the module. In another embodiment, the translator module is attached to a flex-circuit cable coupled to the test system electronics. The translator module is manually placed over each IC package during testing. In a further embodiment, an integrated circuit package contains a built-in test verifier system so that standard test probes can be used to test the package without use of a separate translator module.

    摘要翻译： 安装在装载的印刷电路板（PCB）上的集成电路（IC）封装由翻译器模块测试，首先在每个封装上放置相应的模块。 每个模块具有一排弹簧触点，用于可释放地接触与IC封装相对侧相对应的电引线。 模块的上表面具有内部连接到模块上的相应触点的导电测试焊盘阵列。 测试垫与测试单元中的一组弹簧探针相匹配。 模块可以是具有金属板弹簧触点的模制塑料壳体，或者其可以包括具有包括柔性弹簧状金属化塑料指状物的单独触点的复合柔性电路材料。 测试模块上的触点可以直接可释放地接合IC封装上的引线，或者它们可以接触与IC封装上引线相邻的PCB上的分离的导线。 在测试期间，弹簧探头接触测试模块上的测试焊盘，并通过从弹簧探针通过模块到邻近IC封装的导线的电气连接建立电路连续性。 这些模块将紧邻IC封装的引线的密集在线间距转换为模块上测试焊盘的过大的在线间距。 在另一个实施例中，转换器模块连接到耦合到测试系统电子装置的柔性电路电缆。 翻译器模块在测试期间手动放置在每个IC封装上。 在另一实施例中，集成电路封装包含内置测试验证器系统，使得可以使用标准测试探针来测试封装而不使用单独的转换器模块。

    Noise reduction during testing of integrated circuit chips
    75.
    发明公开
    Noise reduction during testing of integrated circuit chips 失效
    Verminderung des RauschenswährenddesPrüfensvon。

    公开(公告)号：EP0213453A2

    公开(公告)日：1987-03-11

    申请号：EP86110981.7

    申请日：1986-08-08

    申请人： International Business Machines Corporation

    发明人： Davidson, Evan E. ,  Kiesling, David A.

    IPC分类号： G01R31/28 ,  G06F11/26

    CPC分类号： G01R31/316 ,  G01R31/31924 ,  G01R31/3193

    摘要： A test system having improved means for reducing driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit device, such as a logic chip. The integrated circuit device has a plurality of input terminals (R5-R54) for receiving an electrical test pattern from the tester. The integrated circuit device also includes a plurality of output driver circuits (D2-D1O2) having outputs connected to the tester. The test system is characterized in that said integrated circuit device includes a driver sequencing circuit (L1-L1O) responsive to at least one control signal (R1-R4) from said tester to sequentially condition said driver circuits for possible switching, whereby delta I noise is reduced during testing.

    摘要翻译： 一种具有改进的用于减少驱动器切换（ΔI）噪声的装置的测试系统。 测试系统采用连接到电子测试的测试仪器，例如逻辑芯片。 集成电路装置具有用于从测试器接收电测试图案的多个输入端子（R5-R54）。 集成电路装置还包括具有连接到测试器的输出的多个输出驱动器电路（D2-D1O2）。 所述测试系统的特征在于，所述集成电路器件包括响应于来自所述测试器的至少一个控制信号（R1-R4）的驱动器排序电路（L1-L1O），以顺序地调节所述驱动电路以进行可能的切换，由此δI噪声 在测试期间减少。