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    Integrated circuit I/O using a high performance bus interface
    71.
    发明公开
    Integrated circuit I/O using a high performance bus interface 无效

    公开(公告)号：EP1816569A3

    公开(公告)日：2007-09-26

    申请号：EP06125946.1

    申请日：1991-04-16

    申请人： RAMBUS INC.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F13/42

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention includes a system comprising a bus that includes a plurality of bus lines for carrying substantially all address, data and control information needed by each semiconductor device coupled to the bus for communication with substantially every other semiconductor device connected to the bus, wherein the bus uses address multiplexing to convey a single memory address, a plurality of synchronous dynamic random access memory (DRAM) semiconductor devices coupled to the bus, each DRAM of the plurality of synchronous DRAM semiconductor devices including connection means adapted to connect the DRAM to the bus, clock receiver circuitry for receiving a clock signal, a programmable access-time register for storing a value which is representative of a number of clock cycles of the clock signal to transpire after which the DRAM responds to a read request received synchronously with respect to the clock signal, the programmable access-time register being accessible to the bus through the connection means, wherein data is provided to the programmable access-time register over the bus to set the value in the programmable access-time register, a plurality of output drivers for outputting data onto the bus in response to the read request, wherein the output drivers output the data on the bus after the number of clock cycles of the clock signal transpire and synchronously with respect to the clock signal; so that the read request and the corresponding response are separated by the number of clock cycles as selected by the value stored in the programmable access-time register, wherein each output driver of the plurality of output drivers outputs the data onto the bus at a bus cycle data rate that is twice the rate of the clock signal, sense amplifiers used for reading the data from the memory array, wherein when precharge information received over the bus as a part of the read request indicates that a precharge operation should be performed, automatically precharging the sense amplifiers as a part of execution of the read request, and wherein when the precharge information indicates that a precharge operation should not be performed, holding the data in the sense amplifiers; and a master device coupled to the bus, wherein the master provides the value stored in the programmable access time register, issues the read request that includes precharge information, and receives the data output in response to the read request at the bus cycle data rate after the number of clock cycles as selected by the value stored in the programmable access time register.

    Integrated circuit I/O using a high performance bus interface
    73.
    发明公开
    Integrated circuit I/O using a high performance bus interface 失效
    Integrierte E / A-Schaltung，死者Hochleistungsbusschnittstelle benutzt

    公开(公告)号：EP1816570A2

    公开(公告)日：2007-08-08

    申请号：EP06125954.5

    申请日：1991-04-16

    申请人： RAMBUS INC.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F13/16

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention includes a semiconductor device, the semiconductor device comprising connection means adapted to connect the semiconductor device to an external bus which is a part of a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to the external bus, wherein the external bus includes a plurality of bus lines for carrying substantially all address, data, control and device select information needed by the semiconductor device for communication with substantially every other semiconductor device connected to the external bus, and wherein the external bus has substantially fewer bus lines than the number of bits in a single address, wherein each said bus line is a terminated transmission line, and wherein the external bus carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to the semiconductor device, a bus line driver capable of producing a low-voltage-swing signal on one of said terminated transmission lines, wherein the semiconductor device is a semiconductor transceiver device to interface multiple units to the bus, wherein the multiple units are DRAMs.

    摘要翻译： 本发明包括一种半导体器件，该半导体器件包括适于将半导体器件连接到外部总线的连接装置，外部总线是外部总线，外部总线是包括与外部总线并联连接的多个半导体器件的半导体总线架构的一部分，其中外部 总线包括用于承载半导体器件所需的基本上所有地址，数据，控制和器件选择信息的多条总线，用于与连接到外部总线的基本上每个其他半导体器件通信，并且其中外部总线具有比 单个地址中的位数，其中每个所述总线是终止的传输线，并且其中所述外部总线承载所述半导体器件的器件选择信息，而不需要直接连接到半导体器件的单独的器件选择线 ，能够产生低电平的总线线路驱动器 在所述端接的传输线之一上的电压摆动信号，其中所述半导体器件是将多个单元连接到所述总线的半导体收发器设备，其中所述多个单元是DRAM。

    High level message priority assignment by a plurality of message-sending nodes sharing a signal bus
    74.
    发明授权
    High level message priority assignment by a plurality of message-sending nodes sharing a signal bus 有权
    在用于在多个节点的较高级别的消息的公共总线上优先

    公开(公告)号：EP1374489B1

    公开(公告)日：2006-05-10

    申请号：EP02724921.8

    申请日：2002-02-06

    申请人： Honeywell International Inc.

    发明人： NICHOLS, Steven, C.

    IPC分类号： H04L12/413 ,  G06F13/18 ,  G06F13/372

    CPC分类号： G06F13/376 ,  G06F13/374

    摘要： A system has a plurality of nodes communicating with each other on a serial data path using dominant and recessive signal levels. A dominant signal level sent on the data path by any of the nodes creates a dominant signal level on the data path irrespective of the number of recessive signal levels sent by other nodes. The dominant and recessive signal levels form a series of bits organized into messages by the nodes. Each sending node senses the signal level on the data path bit by bit, and if different form that sent by that sending nodes, halts further sending of signal levels by that sending node. A priority value generator in each node provides a priority signal encoding a value whose magnitude indicates a relative priority. A message priority module in each node receives the priority signal, and stores the priority value in predetermined leading bits of the message to be sent.

    Integrated circuit i/o using a high performance bus interface
    77.
    发明公开
    Integrated circuit i/o using a high performance bus interface 无效
    DRAM Halbleiter Vorrichtung

    公开(公告)号：EP0994420A2

    公开(公告)日：2000-04-19

    申请号：EP99118308.8

    申请日：1991-04-16

    申请人： RAMBUS INC.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F13/16

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/00 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14

    摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

    摘要翻译： 本发明包括一个包括至少两个半导体器件（15,16,17）的存储器子系统，包括连接到总线（18）的至少一个存储器件（15,16或17），其中总线包括多个 用于承载所述存储器设备（15,16或17）所需的基本上所有地址，数据和控制信息的总线，其中所述控制信息包括设备选择信息，并且所述总线（18）具有比所述位数更少的总线 在单个地址中，并且总线（18）承载设备选择信息，而不需要直接连接到各个设备的分离的设备选择线路。 本发明还包括用于主设备和从设备在总线（18）上通信的协议，并且用于每个设备中的寄存器以区分每个设备，并允许总线请求被引导到单个或所有设备（15,16,17 ）。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在优选的实施方式中，8个总线数据线和地址有效总线承载地址，数据和控制信息，用于高达40位宽的存储器地址。

    INTEGRATED CIRCUIT I/O USING A HIGH PREFORMANCE BUS INTERFACE
    80.
    发明公开
    INTEGRATED CIRCUIT I/O USING A HIGH PREFORMANCE BUS INTERFACE 无效
    集成电路I / O使用高性能总线接口

    公开(公告)号：EP0525068A1

    公开(公告)日：1993-02-03

    申请号：EP91908374.0

    申请日：1991-04-16

    申请人： RAMBUS INC.

    发明人： FARMWALD, Michael ,  HOROWITZ, Mark

    IPC分类号： G06F1 ,  G06F11 ,  G06F12 ,  G06F13 ,  G11C5 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

    摘要翻译： 本发明涉及包括至少两个半导体器件（15,16,17）的存储器子系统，其中连接到总线（18）的存储器件（15,16或17） 它包含多条总线，用于传送存储设备（15,16或17）所需的基本上所有的地址，数据和控制信息。 控制信息由设备选择信息组成，并且总线（18）具有实质上小于每个地址中的位数的行数，并且总线（18）携带设备选择信息，而没有 有必要将单独设备的选择线直接连接到每个设备。 本发明还涉及到一个协议驱动程序和从属设备，以允许总线（18）和在每个设备的寄存器上的通信操作中，为了区分每个设备和用于引导所述总线请求到单个 或所有设备（15,16,17）。 本发明提供对现有技术装置的修改以实现本发明的新颖特征。 在一个优选实施例中，八条总线数据线和一条地址确认总线线路传送高达40位范围的存储器地址的数据和控制地址信息。